Losing sleep and putting in exorbitant hours lately due to your latest high-speed circuit and the challenge to reach your time to market requirements successfully? One such circuit that is exploding in the consumer market is a DDR circuit.<\/p>\n\n\n\n
DDR RAM or DDR SDRAM is a type of computer memory. It stands for: D<\/strong>ouble D<\/strong>ata R<\/strong>ate S<\/strong>ynchronous D<\/strong>ynamic R<\/strong>andom A<\/strong>ccess M<\/strong>emory. This circuitry is found in all computers. In addition, in today\u2019s consumer electronics markets, it is very common for designers to require this circuitry. The rapid increase in data and multimedia, processing requirements in consumer electronics products has driven significant complexity in the associated memory subsystems. In addition, in this competitive environment time to market factors can include a 6-month design window to achieve production within a 12-month window. This does not leave time for costly design spins to ensure design accuracy. This time crunch and challenge for accuracy can cause great anxiety and leave one awake in the middle of the night and spending many hours in front of the computer. <\/p>\n\n\n\n Reading and deciphering the design rules can be extremely time consuming. One constraint incorrectly entered, and the entire layout can be scrapped and cause an extra design spin and the possibility of missing your market window. Entering the design rules is critical. This should be done by creating a rule on one net, verifying its accuracy, and then copying it with the use of constraint templates to all other similar nets.<\/p>\n\n\n\n Once rules have been entered, it is imperative to check and find the optimal circuit. It\u2019s essential to perform a set of \u201cwhat-if\u201d experiments with your rules. Rather than re-layout the board and then see whether the new layout meets signal integrity (SI) requirements, \u201cWhat-If\u201d analysis can also remedy a common negotiation that takes place between the engineer and a designer. It is not uncommon for an engineer to over-constrain a circuit making it physically impossible for the layout designer to route. This analysis will determine how rules can be relaxed to meet the layout needs while at the same time allowing the circuit to operate with an acceptable tolerance.<\/p>\n\n\n\n At the layout level, a quick method to automate the routing and tuning of these nets accurately to the rules is a must. The manual process of hand stitching routes is no longer an option.<\/p>\n\n\n\n While this article specifically discusses a DDR circuit other high-speed circuits require similar analysis and routing. Examples are Ethernet, and Serdes.<\/p>\n\n\n\n HyperLynx\u00ae LineSim\u00ae provides an environment conducive to quickly changing parameters so that you can test a number of permutations without having to actually lay out each configuration. For example, with HyperLynx\u00ae you can vary line segment length, dielectric constants of materials, and spacing between traces, and explore termination strategies to find the optimal combination for your design. Xpedition Enterprise\u00ae will enable fast rule entry and automated routing and tunning of these nets.<\/p>\n\n\n\n If you\u2019d like to learn the details of using Hyperlynx\u00ae to analyze your designs, you can take our training course Hyperlynx\u00aeSignal Integrity Analysis<\/strong>. It is offered in instructor led<\/a> format by our industry expert instructors and also in a self-paced on-demand<\/a> format. Also, you can now earn a digital badge\/level 1 certificate by taking our Hyperlynx Badging Exam<\/a>. This will enable you to showcase your knowledge of this topic by displaying the badge in your social media and email signature.<\/p>\n\n\n\n If you\u2019d like to learn the details of using Xpedition Enterprise\u00ae to set rules and then automate the routing and tunning to those rules, you can take our training course PCB Advanced Topics<\/strong>. It is offered in instructor led format by our industry expert instructors. It is also in a self-paced on-demand<\/a> format. It can also be tailored to address your specific design goals and show you how to set up an environment for reuse for additional designs. If interested contact<\/a> a Siemens representative. Also, you can now earn a digital badge\/level 1 certificate by taking our Advanced Topics Badging Exam<\/a>. This will enable you to showcase your knowledge of this topic by displaying the badge in your social media and email signature.<\/p>\n\n\n\n Author: Tim Rauscher, Principal Customer Training Engineer, Siemens EDA Learning Services<\/strong><\/p>\n","protected":false},"excerpt":{"rendered":" Losing sleep and putting in exorbitant hours lately due to your latest high-speed circuit and the challenge to reach your…<\/p>\n","protected":false},"author":71643,"featured_media":568,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[350,384,359,324,388,512,387,357],"industry":[],"product":[],"coauthors":[328],"class_list":["post-557","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news","tag-certification","tag-ddr","tag-digital-badge","tag-hyperlynx","tag-pcb","tag-siemens-xcelerator-academy","tag-signal-integrity","tag-training"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/52\/2022\/05\/gehirn_original.jpg","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/posts\/557","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/users\/71643"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/comments?post=557"}],"version-history":[{"count":5,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/posts\/557\/revisions"}],"predecessor-version":[{"id":574,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/posts\/557\/revisions\/574"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/media\/568"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/media?parent=557"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/categories?post=557"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/tags?post=557"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/industry?post=557"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/product?post=557"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/coauthors?post=557"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}