The PDN Decoupling Optimizer<\/em> is AI-powered through a genetic algorithm that takes in an initial LineSim or a BoardSim design, with some capacitors scattered across the IC power pin fields as a start, and reports back to you solutions that are optimized to minimize cost and total number of capacitors, while ensuring that the PDN target impedance requirement is met. The operating principle is that the PDN Decoupling Optimizer<\/em> starts with stripping off, in other words, open-circuiting, any capacitor models in the initial design, and then it examines your decoupling capacitor model libraries to identify the best capacitor to be placed in each capacitor location in your design. Sometimes, the PDN Decoupling Optimizer<\/em> may leave a capacitor location open-circuited, anticipating that removing a certain capacitor is the best decision, which is fundamental in determining whether your PDN is overdesigned or inefficient. The concept is illustrated in the image below, where the first and third capacitor branches should carry capacitor models from your libraries that are best suited to the design requirements, and the second capacitor branch is open-circuited.<\/p>\n\n\n For the PDN Decoupling Optimizer<\/em> to run efficiently and produce feasible solutions, the appropriate library setup and syntax must be in place.<\/p>\n\n\n\n To learn how to set up and perform PDN optimization, our new course, HyperLynx Advanced Power Integrity Analysis<\/strong>, provides you with the information to run the different algorithms, besides the genetic algorithm, that the PDN Decoupling Optimizer offers. This will ensure that your designs meet the highest standards as efficiently as possible.<\/p>\n\n\n\n Additionally, you will learn how to perform power-aware analysis and interpret power-aware IBIS models, which is crucial in applications such as DDR, where timing measurements are influenced by the design quality of the PDN. This is enabled by the HyperLynx PDN & Channel Model Extractor<\/em>, which allows you to simulate Simultaneously Switching Outputs (SSO) and Simultaneously Switching Noise (SSN), via-to-via coupling, and non-ideal signal return paths as shown in the image below.<\/p>\n\n\n Finally, the HyperLynx Advanced Power Integrity Analysis<\/strong> class will teach you how to set up and run thermal analysis on your board and how to account for the thermal behavior of the board when running DC drop analysis using the PI\/Thermal Cosimulation<\/em> feature.<\/p>\n\n\n\n If you\u2019re an experienced user in power integrity analysis with HyperLynx, you can take our on-demand training course HyperLynx Advanced Power Integrity Analysis<\/a> (ModernUX), available now with closed captions in 9 languages for our global audiences. This course is also offered in instructor-led format<\/a> by our industry expert instructors and can be tailored to address your specific design goals. Also, you can now earn a digital badge\/Level 1 certification<\/a> by taking our HyperLynx Advanced Power Integrity Analysis Certification Exam<\/strong>. Your digital badge is the validation that you have acquired the necessary technical skills in the HyperLynx Power Integrity Analysis domain and can be displayed on LinkedIn or in your email signature.<\/p>\n\n\n\n However, if you are a new user looking to get started with power integrity analysis, you can begin by taking the HyperLynx Power Integrity Analysis (Modern UX)<\/strong> course, which is available in both self-paced<\/a> and instructor-led<\/a> formats.<\/p>\n\n\n\n![\"\"](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/52\/2025\/04\/Picture1.png\")
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