{"id":9364,"date":"2013-07-26T15:05:28","date_gmt":"2013-07-26T22:05:28","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=9364"},"modified":"2026-03-27T08:34:54","modified_gmt":"2026-03-27T12:34:54","slug":"walking-in-the-desert-or-drinking-from-a-fire-hose","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2013\/07\/26\/walking-in-the-desert-or-drinking-from-a-fire-hose\/","title":{"rendered":"Walking in the Desert or Drinking from a Fire Hose?"},"content":{"rendered":"

You don\u2019t need a graphic like the one below\u00a0to know that multi-core SoC designs are here to stay.\u00a0 This one happens to be based on ARM\u2019s AMBA 4 ACE architecture which is particularly effective for mobile design applications, offering an optimized mix of high performance processing and low power consumption.\u00a0 But with software\u2019s increasing role in overall design functionality, verification engineers are now tasked with verifying not just proper HW functionality, but proper HW functionality under control of application SW.\u00a0 So how do you verify HW\/SW interactions during system level verification?\"\"<\/a><\/p>\n

\"\"<\/a>\u00a0For most verification teams, the current alternatives are like choosing between a walk through the desert or drinking from a fire hose<\/a>.\u00a0 In the desert, you can manually write test programs in C, compile them and load them into system memory, and then initialize the embedded processors and execute the programs.\u00a0 Seems straightforward, but now try it for multiple embedded cores and make sure you confirm your power up sequence and optimal low power management (remember, we\u2019re testing a mobile market design), correct memory mapping, peripheral connectivity, mode selection, and basically anything that your design is intended to do before its battery runs out.\u00a0 You can get lost pretty quickly.\u00a0 Eventually you remember that you weren\u2019t hired to write multi-threaded software programs, but that there\u2019s an entire staff of software developers down the hall who were.\u00a0 So you boot your design\u2019s operating system, load the SW drivers, and run the design\u2019s target application programs, and fully verify that all\u2019s well between the HW and the SW at the system level.<\/p>\n

But here comes the fire hose.\u00a0 By this time, you\u2019ve moved from your RTL simulator to an emulator, because just simulating Linux booting up takes weeks to months.\u00a0 But what happens when your emulator runs into a system level failure after billions of clock cycles and several days of emulation?\u00a0 There\u2019s no way to avoid full HW\/SW verification at the system level, but wouldn\u2019t it be nice to find most of the HW\/SW interaction bugs earlier in the process, when they\u2019re easier to debug?<\/p>\n

\"\"<\/a><\/p>\n

\u00a0There\u2019s an easier way to bridge the gap between the desert and the fire hose.\u00a0 It\u2019s called \u201cintelligent Software Driven Verification<\/a>\u201d.\u00a0 iSDV automates the generation of embedded C test programs, for multi-core processor execution.\u00a0 These tests generate thousands of high-value processor instructions that verify HW\/SW interactions.\u00a0 Bugs discovered take much less time to debug, and the embedded C test programs can run in both simulation and emulation environments, easing the transition from one to the other.Check out the on-line web seminar at the link below to learn about using intelligent Software Driven Verification\u201d as a way to uncover the majority of your system-level design bugs after RTL level simulation, but before full system level emulation.\u00a0<\/p>\n

http:\/\/www.mentor.com\/products\/fv\/multimedia\/automating-software-driven-hardware-verification-with-questa-infact<\/a><\/p>\n

 <\/p>\n","protected":false},"excerpt":{"rendered":"

You don\u2019t need a graphic like the one below\u00a0to know that multi-core SoC designs are here to stay.\u00a0 This one…<\/p>\n","protected":false},"author":71600,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[457,551,562,718,819,820,827],"industry":[],"product":[],"coauthors":[],"class_list":["post-9364","post","type-post","status-publish","format-standard","hentry","category-news","tag-emulation","tag-intelligent-testbench-automation","tag-itba","tag-simulation","tag-verification","tag-verification-academy","tag-verification-methodology"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/9364","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71600"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=9364"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/9364\/revisions"}],"predecessor-version":[{"id":19755,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/9364\/revisions\/19755"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=9364"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=9364"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=9364"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=9364"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=9364"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=9364"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}