This blog begins the\u00a0process of revealing the 2012 Wilson Research Group\u00a0study findings by first focusing on current design trends. \u00a0Let\u2019s begin by\u00a0examining process geometry adoption trends, as shown in Figure 1.\u00a0 Here, you will see trend\u00a0comparisons between the 2007 Far West Research study (gray line), the 2010 Wilson Research Group study (blue line), and the 2012 Wilson Research Group study (green line).<\/p>\n
Figure 1. Process geometry trends<\/strong><\/p>\n Worldwide, the median process geometry size from the 2007 Far West Research study was about 90nm, while the median process geometry size is about 65nm in 2010. Today, the mean process geometry size for a typical project is about 45nm\u2014although you can see that over a third of projects today are designing below 32nm.<\/p>\n In addition to the industry moving to smaller process geometries, the industry is also moving to larger design\u00a0sizes\u00a0as measured in number of gates of logic and datapath, excluding memories (which should not be a surprise). Figure\u00a02 compares\u00a0design sizes\u00a0from the 2002 Collett study (dark blue line), the 2007 Far West Research study (gray line), the 2010 Wilson Research Group study (light blue line), and the 2012 Wilson Research Group study (green line).<\/p>\n Figure 2. Number of gates of logic and datapath trends, excluding memories<\/strong><\/p>\n The study revealed that about a third of the non-FPGA designs today are less than 5M gates, while a third range in size between 5M to 20M gates, and about a third of all designs are larger than 20M gates.<\/p>\n It’s important to note here that the data on the mean design size trends does not reflect volume in terms of semiconductor production.\u00a0For example, you could have fewer projects designing at a small geometry, yet they have higher volume in terms of production.<\/p>\n In Figure 3, I show the mean design size trends between the 2002 Collett study (dark blue line), the 2007 Far West Research study (gray line), the 2010 Wilson Research Group study (light blue line), and the 2012 Wilson Research Group study (green line). Obviously, gate counts have increased over the years, yet a significant number of designs continue to be developed with smaller (and larger) gate counts as indicated by the mean calculation. Another observation is that, as you would expect, the mean gate count trend is essentially following Moore\u2019s law.<\/p>\n Figure 3. Mean design size trends<\/strong><\/p>\n Figure\u00a04 presents the current\u00a0design implementation trends for non-FPGAs as identified by the survey participants.<\/p>\n <\/strong> Figure 4. Non-FPGA current design implementation trends<\/strong><\/p>\n The data in Figure 4 presents trends in design implementation approaches for non-FPGA designs, ranging\u00a0from the 2002 Collett study (dark blue bar), the 2004 Collet study (dark green bar), \u00a0the 2007 Far West Research study (gray bar), the 2010 Wilson Research Group study (blue bar), and the 2012 Wilson Research Group study (green bar).\u00a0Note that the study seems to indicate that there is a downward trend in standard cell design implementation.<\/p>\n![\"\"](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2013\/05\/Fig-1-1-520x390.gif\")
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