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<\/a>The IEEE Standards Association (SA<\/a>) Standards Board (SASB<\/a>) officially approved the latest SystemVerilog revision, Draft 6, as an IEEE standard.\u00a0 The SASB Review Committee (RevCom) agenda<\/a> and the SASB agenda<\/a> include review and formal approval of the latest work by the IEEE Computer Society Design Automation Standards Committee\u2019s (DASC<\/a>) SystemVerilog Working Group at their December 2012 meeting series.<\/p>\nWhat\u2019s New?<\/h3>\n
For users of Mentor Graphics’ Questa Verification Platform, many of the major SystemVerilog 2012 features can be used today, like multiple inheritance.\u00a0 As Stu and Tom said in their presentation, \u201cThis is BIG!\u201d\u00a0 If you read their full paper, they discuss some ways this new feature might be useful for a UVM <\/a>testbench.<\/p>\n Major work was done to augment the current notion of constraints in SystemVerilog.\u00a0 In past versions of the standard they were known as hard constraints<\/em>.\u00a0 What this meant was all the conditions of the constraints had to be met otherwise there would be an error.\u00a0 There was no built-in method to relax the need to satisfy the constraints.\u00a0 Given the world of multiple constraints is the norm for testbenches today the potential for conflicts between them is high.\u00a0 To alleviate this the SystemVerilog Working Group introduced soft constraints<\/em> to the standard.\u00a0 If you are interested in the details of what was proposed to be added the standard, you can reference the full proposal here<\/a> that is included in the standard.\u00a0 Stu and Tom said that \u201cThis is also a big enhancement!\u201d<\/p>\n IEEE 1800\u2122-2012 has only now been approved.\u00a0 The standard itself is not ready to be published yet.\u00a0 Plans are to have it ready to be published before DVCon 2013<\/a>, which is scheduled for late February 2013.\u00a0 I will\u00a0 share publication information as it becomes available.\u00a0 And, I hope you join me and attend DVCon 2013 where we can plan to celebrate the unveiling of the published standard.<\/p>\n There is much more to the SystemVerilog-2012 story I will share more of that in the months ahead.\u00a0 The global team of experts who have put this together has been an outstanding collection of individuals ranging from producers and suppliers of electronic design automation software to consumers of said technology who have ensured the language can be used to design and verify the most demanding of electronic systems.<\/p>\n Stay tuned!\u00a0 For now, I encourage you to get informed!<\/p>\n","protected":false},"excerpt":{"rendered":" IEEE Std. 1800\u2122-2012 Officially Ratified The IEEE Standards Association (SA) Standards Board (SASB) officially approved the latest SystemVerilog revision, Draft…<\/p>\n","protected":false},"author":71541,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[313,351,366,411,442,516,538,540,607,685,725,732,741,751,768,787],"industry":[],"product":[],"coauthors":[],"class_list":["post-6932","post","type-post","status-publish","format-standard","hentry","category-news","tag-313","tag-assertions","tag-ben-cohen","tag-dasc","tag-dvcon","tag-hard-constraints","tag-ieee-sasb","tag-ieee-sa","tag-muttiple-inheritance","tag-revcom","tag-soft-constraints","tag-standards","tag-stu-sutherland","tag-systemverilog","tag-tom-fitzpatrick","tag-uvm"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/6932","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71541"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=6932"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/6932\/revisions"}],"predecessor-version":[{"id":14615,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/6932\/revisions\/14615"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=6932"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=6932"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=6932"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=6932"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=6932"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=6932"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}![\"\"](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2012\/12\/1800-12-0010-00-DRFT-ieee-p1800-systemverilog-d6-clean_Page_0001.jpg\")
<\/a>The new standard has many new features, numerous clarifications and various corrections to improve the standard and keep pace with electronic system design and verification.\u00a0 DVCon 2012 included a session presentation<\/a>, Keeping Up with Chip \u2013 The Proposed SystemVerilog 2012 Standard Makes Verifying Ever-Increasing Design Complexity More Efficient<\/em>\u201d that detailed the standard.\u00a0 The paper was written by Stuart Sutherland (Sutherland HDL, Inc.) and Tom Fitzpatrick (Mentor Graphics).\u00a0 You can find a copy of the paper here<\/a> at the DVCon 2012 archive and the presentation can be found at Sutherland HDL\u2019s site here<\/a>.<\/p>\nAvailability<\/h3>\n
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<\/a>While the IEEE publication will be the authoritative source on the standard, I have pointed to the presentation and paper by Stu Sutherland and Tom Fitzpatrick for information on the new standard that you can reference now.\u00a0 For those who depend on assertions, you will find SystemVerilog-2012 has a major update with enhancements for properties and sequences in the area of immediate assertions, data type support, argument passing, vacuity definitions, global clock resolution and inferred clocking in sequences and much more.\u00a0 You may find the SystemVerilog Assertions Handbook 3rd Edition<\/em> by Ben Cohen, et. al. to be of value as well.\u00a0 You can find more information about it on Amazon.com here<\/a>.<\/p>\nThe Story Continues\u2026<\/h3>\n