{"id":6251,"date":"2012-05-30T15:37:47","date_gmt":"2012-05-30T22:37:47","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=6251"},"modified":"2026-03-27T08:43:47","modified_gmt":"2026-03-27T12:43:47","slug":"off-to-dac","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2012\/05\/30\/off-to-dac\/","title":{"rendered":"Off to DAC!"},"content":{"rendered":"

Where might our paths cross?<\/h3>\n

It is always challenge to fit all the needed visits in during the Design Automation Conference (DAC<\/a>).\u00a0 If you happen to like some of the same events I attend, then the chances are good our paths might cross in public.<\/p>\n

Saturday and Sunday are busy with an Accellera Systems Initiative board meeting.\u00a0 Split across two days, Accellera board members will meet to conduct traditional business and\u00a0 do some strategic planning in which each board member outlines what they aspire the goals and objectives for the group should be in the coming year.\u00a0 Intel has graciously granted space in their San Francisco offices, so I won\u2019t be around the Moscone Center during the pre-conference setup phase.\u00a0 (By the way, Thank you Intel!)
\nAfter we close the Accellera board meeting on Sunday, I plan to attend the pre-DAC events on Sunday that include the EDAC reception<\/a> (registration required<\/a>) at 6:00pm\u00a0 (San Francisco Marriott, Salon 7) and Gary Smith\u2019s \u201cSunday Night at DAC<\/a>\u201d at 7:00pm (San Francisco Marriott, Salon 6).<\/p>\n

During the conference I will spend most of my time at the Mentor Graphics Verification Academy Booth\u00a0 #1514 and on Wednesday split my time between there and the Accellera Systems Imitative meetings.\u00a0 And just in case you may note that most of my evenings are not scheduled, they are with customer activities.<\/p>\n

\"MentorGraphics-Logo\"<\/a>When the show floor is open, you will find me most of the time at the Verification Academy Booth<\/a> #1514.\u00a0 I will join Mentor\u2019s Harry Foster there were user and partner presentations will be done on UVM applications, updates on Harry\u2019s research results, updates on important verification standards from Mentor\u2019s perspective and more.\u00a0 You are invited to join other verification experts for the Tuesday evening cocktail reception at the Verification Academy Booth.\u00a0 (And the cocktail hour may be just the thing that tis needed before the annual DAC Birds-Of-A-Feather meetings begin to help the conversations start.)<\/p>\n

Verification Academy DAC Schedule<\/a><\/h3>\n\n\n\n\n\n\n\n\n\n
Monday, June 4th <\/strong><\/td>\nTuesday, June 5th<\/strong><\/td>\nWednesday, June 6th<\/strong><\/td>\n<\/tr>\n
\n
10:00 – Simulation and Formal Assertion-Based Verification<\/em><\/h6>\n
Harry Foster, Mentor Graphics<\/h6>\n<\/td>\n
\n
9:30 – Using the UVM Register Layer<\/em>
\nJohn Aynsley, Doulos<\/h6>\n<\/td>\n
\n
10:00 – Bringing UVM to Life<\/em>
\nEllie Burns, Mentor Graphics<\/h6>\n<\/td>\n<\/tr>\n
\n
11:00 – Bringing UVM to Life
\n<\/em>Ellie Burns, Mentor Graphics<\/h6>\n<\/td>\n
\n
10:00 – Generating Coverage Models and Achieving Coverage Closure<\/em>
\nMark Olen, Mentor Graphics<\/h6>\n<\/td>\n
\n
11:00 – Resistance is Futile: Learning to love UVM!<\/em>
\nMike Bartley, Test & Verification Solutions<\/h6>\n<\/td>\n<\/tr>\n
\n
2:00 – Verification of Low Power SoCs with IEEE UPF
\n<\/em>Stephen Bailey, Mentor Graphics<\/h6>\n<\/td>\n
\n
2:00 – Bringing UVM to Life
\n<\/em>Ellie Burns, Mentor Graphics<\/h6>\n<\/td>\n
\n
2:00 – Automating Assertion Based Verification with NextOp and Mentor Graphics<\/em>
\nYunshan Zhu, NextOp<\/h6>\n<\/td>\n<\/tr>\n
\n
3:00 – Evolving Trends in Functional Verification<\/em>
\nHarry Foster, Mentor Graphics<\/h6>\n<\/td>\n
\n
3:00 – Evolving Trends in Functional Verification
\n<\/em>Harry Foster, Mentor Graphics<\/h6>\n<\/td>\n
\n
3:00 – UVM Express<\/em>
\nMike Baird, Willamette HDL, Inc.<\/h6>\n<\/td>\n<\/tr>\n
\n
4:00 – An Introduction to AMBA 4 AXI Coherency Extensions (ACE) and Verification Challenges
\n<\/em>Paul Martin, ARM<\/h6>\n<\/td>\n
<\/td>\n\n
4:00 – Evolving Trends in Functional Verification<\/em>
\nHarry Foster, Mentor Graphics<\/h6>\n<\/td>\n<\/tr>\n
\n
5:00 – Using Rules-Based Integration to Develop a SoC-Level UVM Verification Environment<\/em>
\nDavid Murray, Duolog<\/h6>\n<\/td>\n
\n
5:00 – Meet the Verification Experts Cocktail Reception<\/h6>\n<\/td>\n
<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\"Accellera<\/a>Accellera Systems Initiative will host a set of meetings on Wednesday starting with a luncheon to roll out the Unified Coverage Operability Standard (UCIS).\u00a0 The lunch is free and seating is limited and registration is required.<\/p>\n

Hosted Luncheon and Technical Presentation<\/h3>\n

Accellera Systems Initiative Rolls Out the Unified Coverage Interoperability Standard<\/h4>\n


\n<\/strong>Speaker: Dr. Richard Ho, Co-Chair of the UCIS Technical Subcommittee<\/em><\/p>\n

Wednesday, June 6, 12:00-1:30pm
\nMoscone Center, Room 250
\nRegister Now ><\/a>
\nThis luncheon is open to all DAC attendees. Seating is limited! You must <\/em>pre-register<\/em><\/a> for this event. <\/em><\/p>\n

Coverage metrics are critical to measuring and guiding design verification. As designs have grown, increasingly advanced verification technologies, methods and additional metrics have been designed to form a fuller coverage model. There is currently no single metric that consistently and globally tells engineers the exact status of verification. But one step in the right direction is to bring all types of coverage metrics into a single database that can be accessed in an industry standard way. The UCIS facilitates the creation of a unified coverage database that allows for interoperability of coverage data across multiple tools from multiple vendors.<\/p>\n

This presentation, intended for verification managers and tool developers alike, provides an introduction to and overview of the UCIS and how users plan to utilize it to enhance their verification flows. We provide a survey of many of the commonly-used coverage metrics and how they are modeled in the UCIS. The information that users will be able to access through the UCIS will allow them to write their own applications to analyze, grade, merge and report coverage from one or more databases from one or more tool vendors. We will also discuss the XML-based interchange format of UCIS, which provides a path to exchange coverage databases without requiring a common code library between tools and vendors.<\/p>\n

SystemC User Group Meeting<\/h3>\n

NASCUG XVIII<\/p>\n

North American SystemC User’s Group Meeting
\nWednesday, June 6, 2:00-6:00pm
\nMoscone Center, Room 262
\nRegister Now ><\/a>
\nThis event is open to all DAC attendees. Seating is limited!<\/em><\/p>\n

The North American SystemC Users Group (NASCUG) provides a unique forum for sharing SystemC experiences and knowledge among industry, research and universities. The agenda<\/a>for the event has a lot offer user group attendees.<\/p>\n

Mentor\u2019s Adam Erickson will present An Open-Source, Standards-Based Library for Achieving Interoperability Between TLM Models in SystemC and SystemVerilog.<\/em>\u00a0 Adam\u2019s presentation<\/a> is scheduled to start at 3:00pm.<\/p>\n","protected":false},"excerpt":{"rendered":"

Where might our paths cross? It is always challenge to fit all the needed visits in during the Design Automation…<\/p>\n","protected":false},"author":71541,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[326,409,453,507,732,749,764,779,785,787,820],"industry":[],"product":[],"coauthors":[],"class_list":["post-6251","post","type-post","status-publish","format-standard","hentry","category-news","tag-accellera","tag-dac","tag-edac","tag-gary-smith","tag-standards","tag-systemc","tag-tlm","tag-ucis","tag-upf","tag-uvm","tag-verification-academy"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/6251","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71541"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=6251"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/6251\/revisions"}],"predecessor-version":[{"id":14624,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/6251\/revisions\/14624"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=6251"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=6251"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=6251"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=6251"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=6251"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=6251"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}