{"id":5760,"date":"2012-02-15T05:38:54","date_gmt":"2012-02-15T12:38:54","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=5760"},"modified":"2026-03-27T08:43:55","modified_gmt":"2026-03-27T12:43:55","slug":"uvm-at-dvcon-2012","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2012\/02\/15\/uvm-at-dvcon-2012\/","title":{"rendered":"UVM\u2122 at DVCon 2012"},"content":{"rendered":"

\u201cReady, Set, Deploy\u201d<\/h3>\n

\"Accellera<\/a>The last half year has seen a theme from Accellera Systems Initiative that declares its Universal Verification Methodology (UVM) is ready for design and verification teams to adopt. This theme started with a whitepaper<\/a> from Accellera I authored with two of my peers, Stan Krolikoski from Cadence Design Systems and Yatin Trivedi from Synopsys. A day long UVM tutorial will be featured during \u201cAccellera Day\u201d at DVCon with the same ready, set, deploy<\/em> theme. The UVM tutorial is timely as I have seen UVM gain traction as OVM users transition at the end of their projects and those who have yet to adopt a standardized methodology have likewise begun their adoption.<\/p>\n

\"uvm<\/a>The UVM tutorial starts with an introduction to UVM, concepts of structured verification methodology, base classes, resource configuration management, error handling and report generation. A section on the UVM register package will show how to create and manage stimulus and checking at the register level. Several expert users will show how this fits together in a complex SoC verification environment and relate lessons learned in preparing the transition to UVM, architecting reusable testbenches, debut techniques and use of the TLM 2.0 in real verification environment.<\/p>\n

The tutorial will be presented by expert verification methodology architects and engineers as shown below:<\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n
Speakers:<\/strong><\/td>\nTom Fitzpatrick<\/td>\nMentor Graphics Corp.<\/em><\/td>\n<\/tr>\n
\u00a0<\/td>\nKathleen Meade<\/td>\nCadence Design Systems, Inc.<\/em><\/td>\n<\/tr>\n
\u00a0<\/td>\nAdiel Khan<\/td>\nSynopsys, Inc.<\/em><\/td>\n<\/tr>\n
\u00a0<\/td>\nStephen D’Onofrio<\/td>\nParadigm Works, Inc.<\/em><\/td>\n<\/tr>\n
\u00a0<\/td>\nJohn Aynsley<\/td>\nDoulos<\/em><\/td>\n<\/tr>\n
\u00a0<\/td>\nMark Strickland<\/td>\nCisco Systems, Inc.<\/em><\/td>\n<\/tr>\n
\u00a0<\/td>\nVanessa Cooper<\/td>\nVerilab, Inc.<\/em><\/td>\n<\/tr>\n
\u00a0<\/td>\nJohn Fowler<\/td>\nAdvanced Micro Devices, Inc.<\/em><\/td>\n<\/tr>\n
\u00a0<\/td>\nPeter J. D\u2019Antonio<\/td>\nThe MITRE Corp.<\/em><\/td>\n<\/tr>\n
\u00a0<\/td>\nJustin Refice<\/td>\nAdvanced Micro Devices, Inc.<\/em><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Conference attendees may choose this tutorial or if you wish to attend the tutorial only, DVCon charges a modest fee ($75.00). You can register<\/strong><\/a> here for the day long UVM tutorial.<\/p>\n

More UVM News<\/h3>\n

With 33 exhibitors at DVCon and the heavy functional verification content, what other venue could deliver the potential of breaking UVM news? I invite you to stop by the Mentor Graphics booth were we can share with you the latest in support of UVM. You will find us at booth 801<\/strong><\/a>.<\/p>\n

I look forward to seeing everyone at DVCon!<\/p>\n","protected":false},"excerpt":{"rendered":"

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