{"id":5644,"date":"2011-12-13T17:16:27","date_gmt":"2011-12-14T00:16:27","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=5644"},"modified":"2026-03-27T08:34:23","modified_gmt":"2026-03-27T12:34:23","slug":"instant-replay-for-debugging-soc-level-simulations","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2011\/12\/13\/instant-replay-for-debugging-soc-level-simulations\/","title":{"rendered":"Instant Replay for Debugging SoC Level Simulations"},"content":{"rendered":"

Instant Replay Offers Multiple Views at Any Speed<\/strong><\/p>\n

If you’ve watched any professional sporting event on television lately, you’ve seen the pressure put on referees and umpires.\u00a0 They have to make split-second decisions in real-time, having viewed ultra-high-speed action just a single time.\u00a0 But watching at home on television, we get the luxury of viewing multiple replays of events in question in high-definition super-slow-motion, one frame at a time, and even in reverse.\u00a0 We also get to see many different views of these controversial events, from the front, the back, the side, up close, or far away.\u00a0 Sometimes it seems there must be twenty different cameras at every sporting event.<\/p>\n

Wouldn’t it nice if you could apply this same principle to your SoC level simulations?\u00a0 What if you had instant replay from multiple viewing angles in your functional verification toolbox?\u00a0 It turns out that such a technology indeed exists, and it’s called “Codelink Replay”.<\/p>\n

Codelink Replay enables verification engineers to use instant replay with multiple viewing angles to quickly and accurately debug even the most complex SoC level simulation failures.\u00a0 This is becoming increasingly important, as we see in Harry Foster’s blog series about the 2010 Wilson Research Group Functional Verification Study that over half of all new design starts now contain multiple embedded processors.\u00a0 If you’re responsible for verifying a design with multiple embedded cores such as ARM’s new Cortex A15 and Cortex A7 processors, this technology will have a dramatic impact for you.<\/p>\n

Multi-Core SoC Design Verification<\/strong><\/p>\n

Multi-core designs present a whole new level of verification challenges.\u00a0 Achieving functional coverage of your IP blocks at the RTL level has become merely a pre-requisite now – as they say “necessary but not sufficient”.\u00a0 Welcome to the world of SoC level verification, where you use your design’s software as a testbench.\u00a0 After all, since a testbench’s role is to mimic the design’s target environment, so as to test its functionality, how better to accomplish this than to execute the design’s software against its hardware, albeit during simulation?<\/p>\n

Some verification teams have already dabbled in this world.\u00a0\u00a0 Perhaps you’ve written a handful of tests in C or assembly code, loaded them into memory, initialized your processor, and executed them.\u00a0 This is indeed the best way to verify SoC level functionality including power optimization management, clocking domain control, bus traffic arbitration schemes, driver-to-peripheral compatibility, and more, as none of these aspects of an SoC design can be appropriately verified at the RTL IP block level.<\/p>\n

However, imagine running a software testbench program only to see that the processor stopped executing code two hours into the simulation.\u00a0 What do you do next?\u00a0 Debugging “software as a testbench” simulation can be daunting.\u00a0 Especially when the software developers say “the software is good”, and the hardware designers say “the hardware is fine”.\u00a0 Until recently, you could count on weeks to debug these types of failures.\u00a0 And the problem is compounded with today’s SoC designs with multiple processors running software test programs from memory.<\/p>\n

This is where Codelink Replay comes in.\u00a0 It enables you to replay your simulation in slow motion or fast forward, while observing many different views including hardware views (waveforms, CPU register values, program counter, call stack, bus transactions, and four-state logic) and software views (memory, source code, decompiled code, variable values, and output) – all remaining in perfect synchrony, whether you’re playing forward or backward, single-step, slow-motion, or fast speed.\u00a0 So when your simulation fails, just start at that point in time, and replay backwards to the root of the problem.\u00a0 It’s non-invasive.\u00a0 It doesn’t require any modifications to your design or to your tests.<\/p>\n

Debugging SoC Designs Quickly and Accurately<\/strong><\/p>\n

So if you’re under pressure to make fast and accurate decisions when your SoC level tests fail, you can relate to the challenges faced by professional sports referees and umpires.\u00a0 But with Codelink Replay, you can be assured that there are about 20 different virtual “cameras” tracing and logging your processors during simulation, giving you the same instant replay benefit we get when we watch sporting events on television.\u00a0 If you’re interested to learn more about this new technology, check out the web seminar at the URL below, that introduces Codelink Replay, and shows how it supports the entire ARM family of processors, including even the latest Cortex A-Series, Cortex R-Series, and Cortex M-Series.<\/p>\n

http:\/\/www.mentor.com\/products\/fv\/multimedia\/verifying-complex-soc-designs-with-questa-codelink<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

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