Have you ever wondered how popular the different IEEE standards for electronic design automation are? Have you ever wondered which ones show the least interest? When buying books online, popular book buying websites sites will rank customer purchases. Many newspapers manage lists that you can consult to determine what is the most popular; what has the highest demand. But if you have purchased any IEEE standards, you will know this information is not available from the IEEE Store or the IEEE XPlore platform.<\/p>\n
On May 4th, the IEEE Standards Association<\/a> announced<\/a> its collaboration with Techstreet<\/a> to create the New IEEE Standards Store<\/strong><\/a>.\u00a0 Until now, anyone who wanted to order a single standard had to use a more complex system that even made it hard to share a permanent link to one\u2019s favorite standard with another.\u00a0 Just look at the Accellera homepage<\/a> for an example of where to get the SystemVerilog (IEEE Std. 1800\u2122) standard.\u00a0 At the writing of this blog, it simply points to www.ieee.org<\/a>.\u00a0 [I will share the fact the IEEE\u2019s new site now has fixed links that can now be used to help others find the most current SystemVerilog standard with the Accellera.]<\/p>\n But back to what is the most popular IEEE EDA standards\u2026 Any guesses?<\/p>\n Before I delve into those details, let me say the ranking is just by ordinal.\u00a0 The New IEEE Standards Store shares no information on the actual number of standards purchased.\u00a0 So the difference between #1 and #10 could be just 10 copies.\u00a0 It probably isn\u2019t, but it could be.\u00a0 But talking about #10, why is it even on the list?\u00a0 The IP-XACT standard (IEEE Std. 1685\u2122) is available for free under the IEEE Get Program<\/a>.\u00a0 Under this program you can download a PDF of the IEEE standard for free.\u00a0 If you want a printed version, you can print your own copy from the free one you download.\u00a0 Back in December 2010, Accellera reported that since the IEEE started to offer IP-XACT for free, there had been 1200 downloads.\u00a0 It also looks like many people did not want the hassle to print and simply ordered the print version directly from the IEEE.\u00a0 The other IEEE EDA standard offered free is SystemC\u00a9\u00a0 And this is probably the reason it is in 32nd place.\u00a0 It is very popular in terms of the number of free downloads.<\/p>\n And yes, if you search for the those two standards on the New IEEE Standards Store, you will find you can order print copies there and if you read the small print below, you will see there is a link to take you to the free online versions.<\/p>\n Harry Foster has issued several research reports on the popularity of one language or format the past several months.\u00a0 In his last blog<\/a>, he discussed which of the design and verification languages are ranked high and those, well, not so high.\u00a0 And I guess I feel best to share the correlation between his findings and these more \u201canecdotal\u201d results from the New IEEE Standards Store.\u00a0 I have been party to many at the top standards\u00a0 (Verilog\/SystemVerilog) and party to the \u201cleast highest\u201d (yes, I can\u2019t say the least liked) VITAL 2000.\u00a0 For vindication, I will note that VITAL-95 comes in at #18.\u00a0 In whole, it appears to me that the New IEEE Standards Store ordinal rankings of EDA standards matches the scientific data from the research Harry has reported.<\/p>\n Below is the full ranking of IEEE EDA standards.\u00a0 Where are your favorites?<\/p>\n There is much more to the New IEEE Standards Store than just the rankings of the standards we use in electronic design automation.\u00a0 As I mentioned, it is easier to share fixed links to IEEE standards.\u00a0 And if you want to track IEEE standards development \u2013 and don\u2019t want to have to register your email address with the actual committee developing it just to know when they are done and a standard is ready \u2013 you can register to be notified when a new standard is ready.\u00a0 The New IEEE Standards Store will notify you when a new one is ready.<\/p>\n Check out the short, one minute, video below to learn more about the New IEEE Standards Store.<\/p>\n How do your favorites rank? Have you ever wondered how popular the different IEEE standards for electronic design automation are?…<\/p>\n","protected":false},"author":71541,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[303,306,307,313,528,558,732,749,751,831,833,842],"industry":[],"product":[],"coauthors":[],"class_list":["post-4499","post","type-post","status-publish","format-standard","hentry","category-news","tag-303","tag-1076-4","tag-307","tag-313","tag-ieee","tag-ip-xact","tag-standards","tag-systemc","tag-systemverilog","tag-verilog","tag-vhdl","tag-vital"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/4499","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71541"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=4499"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/4499\/revisions"}],"predecessor-version":[{"id":14637,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/4499\/revisions\/14637"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=4499"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=4499"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=4499"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=4499"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=4499"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=4499"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}\n\n
\n 1<\/td>\n IEEE 1364-2001<\/a><\/td>\n Verilog Hardware Description Language<\/td>\n<\/tr>\n \n 2<\/td>\n IEEE 1800-2009<\/a><\/td>\n SystemVerilog–Unified Hardware Design, Specification, and Verification Language<\/td>\n<\/tr>\n \n 3<\/td>\n IEEE 1076-2002<\/a><\/td>\n VHDL Language Reference Manual<\/td>\n<\/tr>\n \n 4<\/td>\n IEEE 1076-1993<\/a><\/td>\n VHDL Language Reference Manual<\/td>\n<\/tr>\n \n 5<\/td>\n IEEE 1499-1998<\/a><\/td>\n Interface for Hardware Description Models of Electronic Components<\/td>\n<\/tr>\n \n 6<\/td>\n IEEE 1364-1995<\/a><\/td>\n Hardware Description Language Based on the Verilog\u00ae Hardware Description Language<\/td>\n<\/tr>\n \n 7<\/td>\n IEEE 1800-2005<\/a><\/td>\n SystemVerilog: Unified Hardware Design, Specification and Verification Language<\/td>\n<\/tr>\n \n 8<\/td>\n IEEE 1076.2-1996<\/a><\/td>\n VHDL Mathematical Packages<\/td>\n<\/tr>\n \n 9<\/td>\n IEEE 1076.1-1999<\/a><\/td>\n VHDL Analog and Mixed-Signal Extensions<\/td>\n<\/tr>\n \n 10<\/td>\n IEEE 1685-2009<\/a><\/td>\n IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows<\/td>\n<\/tr>\n \n 11<\/td>\n IEEE 1850-2005<\/a><\/td>\n Property Specification Language (PSL)<\/td>\n<\/tr>\n \n 12<\/td>\n IEEE 1076c-2007<\/a><\/td>\n VHDL Language Reference Manual – Procedural Language Application Interface<\/td>\n<\/tr>\n \n 13<\/td>\n IEEE 1164-1993<\/a><\/td>\n Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)<\/td>\n<\/tr>\n \n 14<\/td>\n IEEE 1850-2010<\/a><\/td>\n Property Specification Language (PSL)<\/td>\n<\/tr>\n \n 15<\/td>\n IEEE 1076.6-2004<\/a><\/td>\n VHDL Register Transfer Level (RTL) Synthesis<\/td>\n<\/tr>\n \n 16<\/td>\n IEEE 1801-2009<\/a><\/td>\n Design and Verification of Low Power Integrated Circuits<\/td>\n<\/tr>\n \n 17<\/td>\n IEEE 1481-2009<\/a><\/td>\n Integrated Circuit (IC) Open Library Architecture (OLA)<\/td>\n<\/tr>\n \n 18<\/td>\n IEEE 1076.4-1995<\/a><\/td>\n VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification<\/td>\n<\/tr>\n \n 19<\/td>\n IEEE\/IEC 61691-5-2004<\/a><\/td>\n IEC 61691-5 Ed.1 (IEEE Std 1076.4(TM)-2000): Behavioural Languages – Part 5: Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification<\/td>\n<\/tr>\n \n 20<\/td>\n IEEE 1647-2008<\/a><\/td>\n Functional Verification Language e<\/td>\n<\/tr>\n \n 21<\/td>\n IEEE 1076.1.1-2011<\/a><\/td>\n VHDL Analog and Mixed-Signal Extensions — Packages for Multiple Energy Domain Support<\/td>\n<\/tr>\n \n 22<\/td>\n IEEE\/IEC 61691-7-2009<\/a><\/td>\n Behavioural languages – Part 7: SystemC Language Reference Manual<\/td>\n<\/tr>\n \n 23<\/td>\n IEEE 1076-1987<\/a><\/td>\n VHDL Language Reference Manual<\/td>\n<\/tr>\n \n 24<\/td>\n IEEE 1076.1.1-2004<\/a><\/td>\n VHDL Analog and Mixed-Signal Extensions—Packages for Multiple Energy Domain Support<\/td>\n<\/tr>\n \n 25<\/td>\n IEEE 1076.3-1997<\/a><\/td>\n VHDL Synthesis Packages<\/td>\n<\/tr>\n \n 26<\/td>\n IEEE\/IEC 61523-3-2004<\/a><\/td>\n IEC 61523-3 Ed.1 (IEEE Std 1497(TM)-2001): Delay and Power Calculation Standards – Part 3: Standard Delay Format (SDF) for the Electronic Design Process<\/td>\n<\/tr>\n \n 27<\/td>\n IEEE 1076\/INT-1991<\/a><\/td>\n Interpretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual<\/td>\n<\/tr>\n \n 28<\/td>\n IEEE\/IEC 62531-2007<\/a><\/td>\n IEC 62531 Ed. 1 (2007-11) (IEEE Std 1850-2005): Standard for Property Specification Language (PSL)<\/td>\n<\/tr>\n \n 29<\/td>\n IEEE 1076.6-1999<\/a><\/td>\n VHDL Register Transfer Level Synthesis<\/td>\n<\/tr>\n \n 30<\/td>\n IEEE 1647-2006<\/a><\/td>\n Functional Verification Language “e”<\/td>\n<\/tr>\n \n 31<\/td>\n IEEE\/IEC 61691-6-2009<\/a><\/td>\n Behavioural languages – Part 6: VHDL Analog and Mixed-Signal Extensions<\/td>\n<\/tr>\n \n 32<\/td>\n IEEE 1666-2005<\/a><\/td>\n SystemC\u00ae Language Reference Manual<\/td>\n<\/tr>\n \n 33<\/td>\n IEEE\/IEC 61691-1-1-2004<\/a><\/td>\n IEC 61691-1-1 Ed.1 (IEEE Std 1076(TM)-2002): Behavioural Languages – Part 1-1: VHDL Language Reference Manual<\/td>\n<\/tr>\n \n 34<\/td>\n IEEE 1364-2005<\/a><\/td>\n Verilog Hardware Description Language<\/td>\n<\/tr>\n \n 35<\/td>\n IEEE\/IEC 61691-4-2004<\/a><\/td>\n IEC 61691-4 Ed.1 (IEEE Std 1364(TM)-2001): Behavioural Languages – Part 4: Verilog\u00ae Hardware Description Language<\/td>\n<\/tr>\n \n 36<\/td>\n IEEE 1076.4-2000<\/a><\/td>\n VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n Learn more about the New IEEE Standards Store<\/h3>\n