{"id":4155,"date":"2011-05-12T01:01:11","date_gmt":"2011-05-12T08:01:11","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=4155"},"modified":"2026-03-27T08:44:12","modified_gmt":"2026-03-27T12:44:12","slug":"getting-your-standards-update-dac-2011","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2011\/05\/12\/getting-your-standards-update-dac-2011\/","title":{"rendered":"Getting Your Standards Update @ DAC 2011"},"content":{"rendered":"

The standards developing organizations defining and updating front-end EDA standards will be at DAC in force.\u00a0 And from the looks of if, they are getting an early start to DAC with updates on IEEE<\/a>, Accellera<\/a> and OSCI<\/a> standards at Sunday workshops.\u00a0 The Sunday workshops may be of particular interest to verification engineers interested in UVM and systems designers interested in SystemC AMS.<\/p>\n

Following the workshops, there will be a half-day meeting of the North American SystemC Users Group on Monday where users will share their SystemC experiences.\u00a0 The following morning, Accellera will host its annual DAC breakfast where the UVM users will meet to share their experiences.\u00a0 A lively conversation is expected.<\/p>\n\n\n\n
\n

Sunday \u2013 June 5, 2011<\/h3>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\"UVM<\/a>DAC Workshop on Universal Verification Methodology (UVM) – Verifying Blocks to IP to SOCs and Systems <\/strong><\/p>\n

Time: <\/strong>10:00 AM \u2014 1:00 PM
\nLocation: <\/strong>San Diego Convention Center Room 33A
\nSummary: <\/strong>The Accellera<\/a> Verification IP Technical Subcommittee (VIP-TSC<\/a>), building on over two years of work by verification experts from around the world, released Universal Verification Methodology (UVM) in February 2011. This workshop, presented by expert verification methodology architects and engineers, will provide an example-based overview of UVM to chip and SOC design and verification engineers of all skill levels on the first open-source verification methodology to be fully supported and endorsed by all major EDA vendors, and many end-user and consulting companies.
\nGET MORE DETAILS<\/a><\/strong><\/p>\n

Registration:<\/strong> This is an official DAC sponsored event and DAC registration<\/strong><\/a> required.<\/p>\n

\n

 <\/p>\n

 <\/p>\n

\"systemc_ams\"<\/a>DAC Workshop on Using the Power of the SystemC AMS Extensions<\/strong><\/h3>\n

Time:<\/strong> 10:00 AM \u2014 6:00 PM
\nLocation:<\/strong> San Diego Convention Center Room 33B
\nSummary:<\/strong> Today\u2019s embedded systems interact more and more tightly with the analog physical environment; where digital HW\/SW subsystems become functionally interwoven with analog\/mixed-signal (AMS) blocks such as RF interfaces, power electronics, or sensors and actuators. Examples are software defined radios, sensor networks, automotive applications, or systems for image sensing. This requires new means to model and simulate the interaction between AMS subsystems and HW\/SW subsystems at functional and architecture levels. Especially for this purpose, the SystemC language standard has been extended with powerful AMS capabilities to tackle the challenges in heterogeneous electronic system-level (ESL) design. You will get a good working knowledge of SystemC AMS<\/a> by attending the workshop.
\nGET MORE DETAILS<\/a><\/strong><\/p>\n

Registration:<\/strong> This is an official DAC sponsored event and DAC registration<\/strong><\/a> required.<\/p>\n\n\n\n
\n

Monday \u2013 June 6, 2011<\/h3>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

 <\/p>\n

\"SystemC<\/a><\/strong><\/strong><\/h3>\n

North American SystemC Users Group Meeting<\/strong><\/p>\n

 <\/p>\n

Time: <\/strong>8:30 AM – 12:00 PM
\nLocation: <\/strong>OMNI Hotel
\nRoom Salon AB
\n675 Laurel Street
\nSan Diego, CA 92101
\nSummary: <\/strong>The North American SystemC Users Group\u00a0 explores the newest advancements in sustainable and flexible solutions for system-level design using SystemC.
\nGET MORE DETAILS<\/a><\/strong><\/p>\n

Registration: <\/strong>This event is free and open to all registered DAC attendees. Click here<\/strong><\/a> <\/em>to reserve your seat<\/em><\/p>\n\n\n\n
\n

Tuesday \u2013 June 7, 2011<\/h3>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\"accellera\"<\/a>Accellera Breakfast at DAC: UVM User Experiences<\/em><\/strong><\/p>\n

Time:<\/strong> 7:00 AM \u2013 8:30 AM
\nLocation:<\/strong> San Diego Convention Center Room 25AB
\nSummary: <\/strong>With the introduction of Accellera\u2019s Universal Verification Methodology (UVM) user interest and adoption has been rapidly growing. You are invited to join us and share the experience with fellow users. During the breakfast, you will hear from real users who have migrated to, and\/or applied, the UVM for the first time.\u00a0 Accellera Verification IP Technical Subcommittee (VIP-TSC) participants will provide their insights on UVM. We invite you to take part in the open discussion to foster greater adoption of this important verification standard.
\nGET MORE DETAILS<\/a><\/strong><\/p>\n

Registration: <\/strong>This event is free open to all registered DAC attendees. Click here<\/strong><\/a> <\/em>to reserve your seat<\/em><\/p>\n","protected":false},"excerpt":{"rendered":"

The standards developing organizations defining and updating front-end EDA standards will be at DAC in force.\u00a0 And from the looks…<\/p>\n","protected":false},"author":71541,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[326,339,409,528,620,623,749,787],"industry":[],"product":[],"coauthors":[],"class_list":["post-4155","post","type-post","status-publish","format-standard","hentry","category-news","tag-accellera","tag-ams","tag-dac","tag-ieee","tag-osci","tag-ovm","tag-systemc","tag-uvm"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/4155","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71541"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=4155"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/4155\/revisions"}],"predecessor-version":[{"id":14638,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/4155\/revisions\/14638"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=4155"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=4155"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=4155"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=4155"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=4155"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=4155"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}