{"id":2168,"date":"2011-03-30T17:42:20","date_gmt":"2011-03-31T00:42:20","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=2168"},"modified":"2026-03-27T08:34:03","modified_gmt":"2026-03-27T12:34:03","slug":"part-1-the-2010-wilson-research-group-functional-verification-study","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2011\/03\/30\/part-1-the-2010-wilson-research-group-functional-verification-study\/","title":{"rendered":"Part 1: The 2010 Wilson Research Group Functional Verification Study"},"content":{"rendered":"

<\/a>Design Trends<\/h3>\n

In my previous blog, I introduced the 2010 Wilson Research Group Functional Verification Study (click here<\/a>). The\u00a0objective of my previous blog was to provide a background\u00a0on this large, worldwide industry study. The key findings\u00a0from this study will be presented in a set of upcoming blogs.\u00a0<\/p>\n

This blog begins the\u00a0process of revealing the 2010 Wilson Research Group\u00a0study findings by first focusing on current design trends. \u00a0Let’s begin by\u00a0examining process geometry adoption trends, as shown in Figure 1.\u00a0 Here, you will see trend\u00a0comparisons between the 2007 Far West Research study (in blue), and the 2010 Wilson Research Group study (in green).<\/p>\n

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Figure 1. Process geometry trends<\/strong><\/p>\n

Worldwide, the median process geometry size from the 2007 Far West Research study was about 90nm.\u00a0 While today the median process geometry size is about 65nm. Regionally, Asia seems to be a little more aggressive in its move to smaller process geometries, where the median process geometry size was found to be 45nm.<\/p>\n

In addition to the industry moving to smaller process geometries, the industry is also moving to larger design\u00a0sizes\u00a0as measured in number of gates of logic and datapath, excluding memories (which should not be a surprise). Figure\u00a02 compares\u00a0design sizes\u00a0from the 2002 Collett study (in orange), the 2007 Far West Research study (in blue), and the 2010 Wilson Research Group study (in green).<\/p>\n

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Figure 2. Number of gates of logic and datapath trends, excluding memories<\/strong><\/p>\n

The study revealed that about 30 percent of the IC\/ASIC designs today are less than 1M gates, while 40 percent range in size between 1M to 20M gates, and about 30 percent of all designs are larger than 20M gates.<\/p>\n

When compiling and\u00a0analyzing the data from the study, in addition to calculating the mean on various aspects of the data, I decided to calculate the median for trend analysis. In Figure 3, I show the median design size trends between the 2002 Collett <\/span><\/span>study (in orange), the 2007 Far West Research study (in blue), and the 2010 Wilson Research Group study (in green). My objective in <\/span>calculating<\/span> the <\/span>median is that\u00a0the resulting value\u00a0partitions the data into equal halves,\u00a0and enables us to easily\u00a0see that half the designs developed today are less than 6.1M gates, while the other half are greater than 6.1M gates.\u00a0Obviously, we can see that gate counts have increased over the years, yet there is still a significant number of designs being developed with smaller gate counts as indicated by the median calculation.<\/span><\/p>\n

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Figure 3. Median design size trends<\/strong><\/p>\n

Figure\u00a04 presents the current\u00a0design implementation approaches as identified by the survey participants, which includes both FPGA and non-FPGA implementations.\u00a0<\/p>\n

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\"p1-slide41\"<\/a>Figure 4. Current design implementation approach<\/strong><\/p>\n

The data in Figure 4 presents trends in design implementation approaches for non-FPGA designs, ranging\u00a0from the 2002 Collett study (in pink), the 2004 Collet study (in orange), \u00a0the 2007 Far West Research study (in blue), and the 2010 Wilson Research Group study (in green).\u00a0The study seems to indicate that there is a downward trend in standard cell design implementation.<\/p>\n

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Figure 5. Non-FPGA design implementation trends<\/strong><\/p>\n

We are not able to present trends for FPGA implementations, since none of the\u00a0prior studies included FPGA survey participants.<\/p>\n

In my next blog (click here<\/a>), I’ll continue discussing current design trends, focusing specifically on embedded processors, power, and clock domains.<\/p>\n","protected":false},"excerpt":{"rendered":"

Design Trends In my previous blog, I introduced the 2010 Wilson Research Group Functional Verification Study (click here). The\u00a0objective of…<\/p>\n","protected":false},"author":71592,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[506,819],"industry":[],"product":[],"coauthors":[],"class_list":["post-2168","post","type-post","status-publish","format-standard","hentry","category-news","tag-functional-verification","tag-verification"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/2168","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71592"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=2168"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/2168\/revisions"}],"predecessor-version":[{"id":19732,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/2168\/revisions\/19732"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=2168"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=2168"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=2168"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=2168"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=2168"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=2168"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}