It struck me that the title was tending towards the allegoric, if not mostly there, due to it conjuring possible metaphoric, astrological meaning as I began to wonder if planetary positioning was going to be offered on the next slide to bolster SystemVerilog\u2019s ascendancy.\u00a0 I asked myself: Is SystemVerilog\u2019s \u201cascendancy\u201d a move to a new spiritual level?\u00a0 Has it transcended all other languages to garner greater social importance for design and verification?\u00a0 Is this a greater representation of another trends?\u00a0 Or, perhaps, I was having a flashback to the hippie era.\u00a0 After all, I was hearing in my mind that Hair song with the phrase<\/p>\n
When the moon is in the second house But I was too young in the hippie era of 1967 to have a real flashback.\u00a0 And Wally\u2019s keynote was not some hippie mumbo jumbo.\u00a0 I am also more than certain any of the engineers in the room at DVCon with some physics background could tell us Jupiter aligns with Mars several times a year and the few who might have astrological training (I\u2019ve got to meet them!) could share with us the Moon is in the 7th House for about two hours every day.<\/p>\n Wally\u2019s DVCon 2011 keynote was presented in three parts.\u00a0 The third and last part was on language transitions.\u00a0 When he got to that section he started it by presenting a slide on language transition titled \u201cSystemVerilog in the Ascendancy.\u201d<\/p>\n When some things go up, others go down.\u00a0 It is no surprise that VERA, which seeded the SystemVerilog standard, has reached a low level of predicted use in 2011 of 3%.\u00a0 Joining this decline is the other language of that day that battled with VERA, \u201ce.\u201d\u00a0 \u201ce\u201d use was at 16% in 2007 and 15% in 2010, but users plan a greater than 25% reduction in use from 2010 to 2011.\u00a0 This is a rather dramatic drop in one year, given it has held so steady from 2007 until now.<\/p>\n Wally also touched on the adoption trends in testbench base-class libraries.\u00a0 Accellera\u2019s UVM shows the largest growth from 2010 use to predicted use in 2011.\u00a0 It should grow from 7% to 27% in the next 12 months.\u00a0 While many projects adopted UVM\u2019s progenitor, OVM, there appears to be no let up in use of OVM either over the next 12 months.\u00a0 In fact, there is some small growth predicted from 42% to 47%.\u00a0 Ongoing projects are the most probable reason that the OVM transition to UVM does not appear to start in the next 12 months.\u00a0 One can postulate that once projects end, teams can consider a transition from OVM to UVM.\u00a0 What it means to Mentor, OVM support is going to be critical for customer success for some time. What is declining?\u00a0 \u201cOther methodologies,\u201d such as in-house or homebrew drop fastest as the last holdouts adopt the Accellera industry standard.\u00a0 All the other methodologies show small declines in the coming year.<\/p>\n The survey results Wally shared confirm the world is tending towards dominant use of IEEE Std. 1800\u2122 (SystemVerilog) and Accellera UVM\u2122.\u00a0\u00a0 If the world is aligning on these standards, can we predict the standards wars are over?\u00a0 Looks like another Hair musical flashback:<\/p>\n Then peace will guide the planets. There are more survey results in Wally\u2019s keynote.\u00a0 I will offer additional commentary in subsequent posts.\u00a0 Maybe you see additional information and meaning in those numbers.\u00a0 If so, I invite you to share your views and opinions of them.\u00a0 And no, you don\u2019t need to dim the lights, turn on the black lights, download and listen to Hair\u2019s Aquarius to divine your view.<\/p>\n","protected":false},"excerpt":{"rendered":" Wally Rhines DVCon 2011 Keynote Highlights Survey on Verification Languages OK, maybe it is not the Dawning of the Age…<\/p>\n","protected":false},"author":71541,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[442,623,751,787,819,833,846],"industry":[],"product":[],"coauthors":[],"class_list":["post-2108","post","type-post","status-publish","format-standard","hentry","category-news","tag-dvcon","tag-ovm","tag-systemverilog","tag-uvm","tag-verification","tag-vhdl","tag-wally-rhines"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/2108","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71541"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=2108"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/2108\/revisions"}],"predecessor-version":[{"id":14641,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/2108\/revisions\/14641"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=2108"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=2108"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=2108"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=2108"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=2108"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=2108"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
\nand Jupiter aligned with Mars\u2026<\/em><\/p>\n![\"DVCon](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2011\/03\/dvcon-2011-keynotefinal-030111.jpg\")
<\/a>When Wally last keynoted DVCon in 2008, he presented information that SystemVerilog had been adopted by 24% of survey respondents in 2007.\u00a0 For 2010 that number is 60% and will be 74% in 2011.<\/p>\n![\"DVCon](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2011\/03\/dvcon-2011-keynotefinal-030111-56.jpg\")
<\/a>Wally also discussed the adoption of languages by geography.\u00a0 SystemVerilog has a strong global presence with particular strength in Asia and India.\u00a0 The \u201ce\u201d language shows focused geographic use in Europe\/Israel followed by India.\u00a0 VHDL\u2019s use also has focused geographic use with Europe\/Israel leading followed by North America.\u00a0 It is interesting to note some languages have broad global appeal while others have only regional adoption.<\/p>\n![\"DVCon](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2011\/03\/dvcon-2011-keynotefinal-030111-57.jpg\")
<\/a><\/p>\n
\nAnd love will steer the stars<\/em><\/p>\n