{"id":19495,"date":"2025-09-08T17:33:43","date_gmt":"2025-09-08T21:33:43","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/?p=19495"},"modified":"2026-03-27T08:53:57","modified_gmt":"2026-03-27T12:53:57","slug":"the-grapes-are-back-and-cake-and-c-tests-with-uvm-and-transactions-for-all-easy","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2025\/09\/08\/the-grapes-are-back-and-cake-and-c-tests-with-uvm-and-transactions-for-all-easy\/","title":{"rendered":"The Grapes Are Back! And Cake! And C Tests with UVM and Transactions For All! Easy."},"content":{"rendered":"\n

The grapes have returned – this weekend was “harvest” time. Jelly everywhere. A lot like this year here at Siemens. Lots of activity. New products. Announcements. Products everywhere. Jelly everywhere.<\/p>\n\n\n\n

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California Wild Grapes Boiling<\/figcaption><\/figure>\n\n\n\n

We’ve had a big year with our Questa One<\/a> Launch, lots of things going on and lots of great new products.<\/h2>\n\n\n\n

But today is about going back to DVCON Japan 2024 and DVCON Japan 2025<\/a> (just completed). Before we get to “cake” and transactions and all the rest, don’t forget – DVCON Taiwan 2025<\/a> and DVCON India 2025<\/a> are both this week – hopefully if you’re in the area you’ll stop by and check-out all the new things at our booth – and maybe attend some presentations.<\/p>\n\n\n\n

C Tests with UVM<\/h3>\n\n\n\n

For me, DVCON Japan 2024, was about “Having Your Cake and Eating It Too – Programming UVM Sequences with C Code” with Tomoki Watanabe. It was a romp through connecting C code to UVM sequences using a mapping in an interface. Not as hard as it sounds, with some diagrams, explanations and example source code.<\/p>\n\n\n\n

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C Code Connected To Sequences<\/figcaption><\/figure>\n\n\n\n

The idea being – have your cake and eat it too – have your standard UVM verification environment, and have your C verification environment connected. Have C tests running at the same time as UVM tests – sharing the same sequencer and driver.<\/p>\n\n\n\n

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Threads rendered as transactions<\/figcaption><\/figure>\n\n\n\n

Correlation with Transactions in the Wave Window<\/h3>\n\n\n\n

DVCON Japan 2025 was about “SystemVerilog Transactions, UVM and C – Correlation in a functional verification environment” – Correlation in the wave window using transactions. <\/p>\n\n\n\n

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Correlating Transactions In The Wave Window<\/figcaption><\/figure>\n\n\n\n

In the paper with Tomoki Watanabe, we demonstrate how valuable correlated data is – and that the wave window is a great place to correlate things – by time. But the neatest part is that we correlated C code, UVM sequences and tests, VHDL, Memory reads and writes, Gate level designs using bind, and even backdoor access. The wave window correlation is with transactions – so most of the “places” above needed some transaction recording instrumentation. It’s real easy to do, and quite valuable for debug and verification.<\/p>\n\n\n\n

I know that’s a lot. But the visibility is worth it. It was an exciting two years at DVCON worldwide and at Siemens EDA with our Questa One<\/a>.<\/p>\n\n\n\n

See you next time. Have fun verifying…<\/p>\n\n\n\n

Links<\/h3>\n\n\n\n

Papers and Presentations can be found at<\/p>\n\n\n\n