{"id":19491,"date":"2025-09-03T10:51:03","date_gmt":"2025-09-03T14:51:03","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/?p=19491"},"modified":"2026-03-27T08:53:55","modified_gmt":"2026-03-27T12:53:55","slug":"why-first-silicon-success-is-getting-harder-for-system-companies","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2025\/09\/03\/why-first-silicon-success-is-getting-harder-for-system-companies\/","title":{"rendered":"Why First-Silicon Success Is Getting Harder for System Companies"},"content":{"rendered":"\n

Everyone wants their own chip. Few are hitting first-silicon success.<\/em><\/p>\n\n\n\n

That\u2019s the paradox shaping today\u2019s semiconductor landscape.<\/p>\n\n\n\n

In the 2024 Siemens EDA \/ Wilson Research Group Functional Verification Study<\/strong>, which I authored, we found that only 14% of ASIC\/SoC projects achieved first-silicon success<\/strong> \u2014 the lowest figure in more than twenty years of tracking this data.<\/p>\n\n\n\n

The decline is industry-wide, but it\u2019s especially pronounced among system companies<\/strong>: automotive OEMs, hyperscalers, and consumer brands that once purchased chips are now designing their own. The logic is sound \u2014 custom silicon promises differentiation, control over performance, and tighter vertical integration. But the results highlight a hard truth: designing chips is far more unforgiving than many anticipated.<\/p>\n\n\n\n

The Experience Gap<\/h3>\n\n\n\n

Chip design is not just about brilliant engineers; it\u2019s about accumulated knowledge. Traditional semiconductor firms spent decades building \u201cmuscle memory\u201d around flows, sign-off criteria, and coverage closure. They know from experience which corner cases sink projects and how to structure verification to catch them.<\/p>\n\n\n\n

System companies, despite hiring top technical talent, are starting without that playbook. Even small oversights in methodology can lead to multimillion-dollar respins. And at today\u2019s advanced nodes, a single respin can wipe out an entire product cycle.<\/p>\n\n\n\n

Cultural Clashes<\/h3>\n\n\n\n

Software-first organizations often thrive on iteration. The mantra of \u201cship fast, patch later\u201d has worked well in the app or cloud world. But silicon is different. At 3nm, a mask set costs tens of millions of dollars. Launch schedules are tightly coupled to vehicles, phones, and data centers. There is no \u201cpatch later\u201d when the product is hardware.<\/p>\n\n\n\n

This cultural adjustment \u2014 from moving fast to verifying relentlessly \u2014 is proving more challenging than many system companies expected.<\/p>\n\n\n\n

Verification Reality<\/h3>\n\n\n\n

Our study data continues to underline a consistent truth: 60\u201370% of engineering effort in chip projects belongs in verification<\/strong>. Traditional chipmakers have internalized this, pouring resources into testbenches, emulation, and coverage analysis.<\/p>\n\n\n\n

By contrast, many system companies underestimate verification at the outset. They view it as overhead rather than the lifeblood of silicon success. The result is predictable: bugs escape pre-silicon, only to surface in the lab. That gap is one of the biggest contributors to today\u2019s lower first-silicon success rates.<\/p>\n\n\n\n

Safety and Standards Pressure<\/h3>\n\n\n\n

For automotive OEMs, the challenge is even steeper. Standards such as ISO 26262 demand safety mechanisms, redundancy, fault injection handling, and comprehensive corner-case analysis. These requirements dramatically expand the verification state space \u2014 at precisely the time when organizations are still climbing the silicon learning curve.<\/p>\n\n\n\n

The complexity of meeting safety standards cannot be overstated. It turns out that designing a chip<\/em> is one thing, but designing a chip that passes rigorous functional safety requirements is another challenge entirely.<\/p>\n\n\n\n

The Bigger Picture<\/h3>\n\n\n\n

Of course, it isn\u2019t just about new players. Even seasoned semiconductor firms are under pressure. Advanced packaging, chiplet-based integration, EUV lithography variability, power integrity, and high-speed protocol complexity have all contributed to the industry-wide decline in first-silicon success.<\/p>\n\n\n\n

But system companies amplify the effect. They are learning these lessons in real time, at the very moment when the economics of failure are harsher than ever.<\/p>\n\n\n\n

Closing the Gap<\/h3>\n\n\n\n

The democratization of silicon design is a positive trend. It encourages innovation, enables differentiation, and creates opportunities for industries that once relied on off-the-shelf components.<\/p>\n\n\n\n

But custom silicon is unforgiving. To succeed, companies must combine strong design talent with organizational maturity, disciplined verification methodologies, and respect for the economic impact of a respin<\/strong>.<\/p>\n\n\n\n

This is exactly why Siemens is investing in solutions like\u00a0Questa One<\/a><\/strong>\u00a0\u2014 to unify and accelerate verification \u2014 and why we created the\u00a0Verification Academy<\/strong><\/a>\u00a0\u2014 to help build the skills our industry desperately needs. <\/p>\n\n\n\n

The data is clear: first-silicon success is harder than it looks. But with the right tools and the right skills, it\u2019s absolutely achievable.<\/p>\n\n\n\n

<\/p>\n","protected":false},"excerpt":{"rendered":"

First-silicon success is getting harder.<\/p>\n

Everyone wants their own chip. Few are hitting first-silicon success.<\/p>\n

That\u2019s the paradox shaping today\u2019s semiconductor landscape.<\/p>\n

In the 2024 Siemens EDA \/ Wilson Research Group Functional Verification Study, which I authored, we found that only 14% of ASIC\/SoC projects achieved first-silicon success \u2014 the lowest figure in more than twenty years of tracking this data.<\/p>\n","protected":false},"author":71592,"featured_media":19412,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[986,985,987,7,10],"tags":[506,1631,820,851],"industry":[32,39,53],"product":[205],"coauthors":[967],"class_list":["post-19491","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-fusa","category-do-254","category-iso-26262","category-learning-resources","category-tips-tricks","tag-functional-verification","tag-questa-one","tag-verification-academy","tag-wilson-research-group-functional-verification-study","industry-aerospace-defense","industry-automotive-transportation","industry-electronics-semiconductors","product-questa"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2025\/06\/SIMATIC-AX-1337_original-scaled.jpg","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/19491","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71592"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=19491"}],"version-history":[{"count":3,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/19491\/revisions"}],"predecessor-version":[{"id":19511,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/19491\/revisions\/19511"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media\/19412"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=19491"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=19491"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=19491"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=19491"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=19491"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=19491"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}