{"id":19457,"date":"2025-08-25T12:05:32","date_gmt":"2025-08-25T16:05:32","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/?p=19457"},"modified":"2026-03-27T08:53:52","modified_gmt":"2026-03-27T12:53:52","slug":"reminder-dvcon-u-s-2026-call-for-papers-sept-7th-deadline-approaching","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2025\/08\/25\/reminder-dvcon-u-s-2026-call-for-papers-sept-7th-deadline-approaching\/","title":{"rendered":"Reminder: DVCon U.S. 2026 Call for Papers \u2013 Sept 7th Deadline Approaching!"},"content":{"rendered":"\n<p>The\u00a0<strong><a href=\"https:\/\/dvcon.org\/submission-instructions\/call-for-extended-abstracts\" data-type=\"link\" data-id=\"https:\/\/dvcon.org\/submission-instructions\/call-for-extended-abstracts\" target=\"_blank\" rel=\"noopener\">DVCon U.S. 2026 Call for Papers<\/a><\/strong>\u00a0deadline is\u00a0<strong>Sunday, September 7th at 11:59 PM<\/strong>. Don\u2019t miss your chance to share your expertise and help shape the future of design and verification.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>What\u2019s New This Year?<\/strong><\/h2>\n\n\n\n<p>DVCon U.S. 2026 will be held at a\u00a0<strong>new, larger venue \u2013 the <a href=\"https:\/\/dvcon.org\/venue-accommodations\" data-type=\"link\" data-id=\"https:\/\/dvcon.org\/venue-accommodations\" target=\"_blank\" rel=\"noopener\">Hyatt Regency Santa Clara<\/a> \u2013 from March 2\u20135, 2026<\/strong>. There will be more space, more networking, and more opportunities to showcase your work!<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Topic Categories Include:<\/strong><\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Verification &amp; Validation<\/strong>\u00a0\u2013 Methodologies, testbenches, coverage, and more.<\/li>\n\n\n\n<li><strong>Design &amp; Modeling<\/strong>\u00a0\u2013 RTL, high-level design, and modeling techniques.<\/li>\n\n\n\n<li><strong>Formal Methods<\/strong>\u00a0\u2013 Property checking, equivalence checking, and formal verification.<\/li>\n\n\n\n<li><strong>Low Power Design &amp; Verification<\/strong>\u00a0\u2013 Techniques for energy-efficient systems.<\/li>\n\n\n\n<li><strong>Mixed-Signal Design &amp; Verification<\/strong>\u00a0\u2013 Bridging analog and digital worlds.<\/li>\n\n\n\n<li><strong>Functional Safety &amp; Security<\/strong>\u00a0\u2013 Safety-critical systems and secure design.<\/li>\n\n\n\n<li><strong>Standards &amp; Interoperability<\/strong>\u00a0\u2013 UVM, SystemVerilog, SystemC, and beyond.<\/li>\n\n\n\n<li><strong>Emerging Trends<\/strong>\u00a0\u2013 New paradigms and methodologies shaping the future.<\/li>\n<\/ul>\n\n\n\n<p><strong>Notice something missing?<\/strong>\u00a0There\u2019s no dedicated\u00a0<strong>AI\/ML category<\/strong>. But don\u2019t let that stop you! If your neural net dreams of closing coverage gaps or your LLM wants to write assertions,\u00a0<strong>we want to hear about it<\/strong>. Just tie it to an existing category\u2014AI for low-power optimization? ML for formal property generation? Go for it! (Just don\u2019t let your AI submit the paper for you\u2026 yet.) [<em>Disclaimer<\/em>&#8211; I asked GPT-5 to help write that last paragraph\ud83e\udd13]<\/p>\n\n\n\n<p>Hope to see you in person March 2-5, 2026 in Santa Clara,CA,<\/p>\n\n\n\n<p>Dave Rich<br>DVCon US 2026 Program Chair<br><a href=\"https:\/\/learn.sw.siemens.com\/public\/eda-one-glance\/oneglance.pdf#page=24\" target=\"_blank\" rel=\"noopener\">Functional Design and Verification Learning Services<\/a><\/p>\n\n\n\n<p><\/p>\n","protected":false},"excerpt":{"rendered":"<p>The\u00a0DVCon U.S. 2026 Call for Papers\u00a0deadline is\u00a0Sunday, September 7th at 11:59 PM. Don\u2019t miss your chance to share your expertise&#8230;<\/p>\n","protected":false},"author":71689,"featured_media":19458,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1,5,982,10,983],"tags":[326,1633,486,488,506,732,749,751,1607,787],"industry":[1564,53],"product":[205,1606,206,207,1091,208],"coauthors":[1232],"class_list":["post-19457","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news","category-events","category-systemverilog","category-tips-tricks","category-uvm","tag-accellera","tag-ai-in-eda","tag-formal","tag-formal-apps","tag-functional-verification","tag-standards","tag-systemc","tag-systemverilog","tag-systemverilog-assertions","tag-uvm","industry-electronic-design-automation","industry-electronics-semiconductors","product-questa","product-questa-formal","product-questa-verification-ip","product-questa-verification-ip-oem-editions","product-questa-verification-iq","product-questasim-oem-editions"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2025\/08\/large_dvconus26_logo_hr_color_edd3e9f0c4.png","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/19457","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71689"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=19457"}],"version-history":[{"count":4,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/19457\/revisions"}],"predecessor-version":[{"id":19462,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/19457\/revisions\/19462"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media\/19458"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=19457"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=19457"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=19457"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=19457"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=19457"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=19457"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}