{"id":19426,"date":"2025-07-31T11:20:07","date_gmt":"2025-07-31T15:20:07","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/?p=19426"},"modified":"2026-03-27T08:53:50","modified_gmt":"2026-03-27T12:53:50","slug":"siemens-eda-at-fms-2025-shaping-the-future-of-memory-and-storage","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2025\/07\/31\/siemens-eda-at-fms-2025-shaping-the-future-of-memory-and-storage\/","title":{"rendered":"Siemens EDA at FMS 2025 \u2013 Shaping the Future of Memory and Storage"},"content":{"rendered":"\n<h2 class=\"wp-block-heading\"><strong>Join Siemens EDA at the Future of Memory and Storage Conference, August 5\u20137, 2025, in Santa Clara, CA<\/strong><\/h2>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"alignright size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"489\" height=\"300\" src=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2025\/07\/blue-no-words.png\" alt=\"\" class=\"wp-image-19435\"\/><\/figure><\/div>\n\n\n<p>Siemens EDA is proud to be a featured participant at the&nbsp;<strong><a href=\"https:\/\/futurememorystorage.com\/\" target=\"_blank\" rel=\"noopener\">Future of Memory and Storage (FMS) 2025<\/a><\/strong>&nbsp;conference, taking place at the&nbsp;<strong>Santa Clara Convention Center<\/strong>. As a leader in verification IP and system-level solutions, Siemens EDA will showcase cutting-edge innovations across CXL, UCIe, NVMe, and AI interconnect technologies.<\/p>\n\n\n\n<p>Visit us at&nbsp;<strong>Booth #1140<\/strong>&nbsp;to explore how our solutions accelerate time-to-market, enhance interoperability, and ensure robust system-level verification for next-generation memory and storage architectures.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Don\u2019t Miss These Siemens EDA Presentations<\/strong><\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong><span style=\"text-decoration: underline;\"><a href=\"https:\/\/futurememorystorage.com\/program\/program-at-a-glance?date=2025-08-05\" target=\"_blank\" rel=\"noopener\">Tuesday, August 5<\/a><\/span><\/strong><br><mark style=\"background-color:#20c997\" class=\"has-inline-color\">\ud83d\udd57<\/mark>\u00a0<strong>8:30\u20139:30 AM | Ballroom C<\/strong><br><strong>CXL Security Stack Verification and its Challenges<\/strong><br><em>Presented by PJ Wang (on behalf of Richa Gupta)<\/em><br>Explore the full CXL security stack\u2014from SPDM to IDE and TSP\u2014and the verification strategies needed to secure data against physical attacks and unauthorized access.<\/li>\n<\/ul>\n\n\n\n<p><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong><span style=\"text-decoration: underline;\"><a href=\"https:\/\/futurememorystorage.com\/program\/program-at-a-glance?date=2025-08-06\" target=\"_blank\" rel=\"noopener\">Wednesday, August 6<\/a><\/span><\/strong><br><mark style=\"background-color:#20c997\" class=\"has-inline-color\">\ud83d\udd58<\/mark>\u00a0<strong>8:30\u20139:35 AM | Ballroom B<\/strong><br><strong>Revolutionizing Memory for AI\/ML\u2019s Future: MRDIMM<\/strong><br><em>Presented by Pankaj Goel<\/em><br>Discover how MRDIMM delivers higher bandwidth, lower latency, and energy efficiency\u2014key enablers for AI\/ML workloads.<br> <br><mark style=\"background-color:#20c997\" class=\"has-inline-color\">\ud83d\udd59<\/mark>\u00a0<strong>9:45\u201310:50 AM | Ballroom G<\/strong><br><strong>Software Aware Verification IP for CXL, NVMe, UCIe<\/strong><br><em>Presented by Luis E. Rodriguez<\/em><br>Learn how Siemens\u2019 platform bridges firmware, software, and hardware teams using open-source tools and SystemC for early system-level validation.<\/li>\n<\/ul>\n\n\n\n<p><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong><span style=\"text-decoration: underline;\"><a href=\"https:\/\/futurememorystorage.com\/program\/program-at-a-glance?date=2025-08-07\" target=\"_blank\" rel=\"noopener\">Thursday, August 7<\/a><\/span><\/strong><br><mark style=\"background-color:#20c997\" class=\"has-inline-color\">\ud83d\udd58<\/mark>\u00a0<strong>9:45\u201310:50 AM | Ballroom C<\/strong><br><strong>Pre-Migration Verification for NVMe SSDs: Ensuring Seamless Live Migration<\/strong><br><em>Presented by Prashant Dixit<\/em><br>Gain insights into verifying NVMe live migration with reusable APIs, UVM features, and compliance test suites.<br> <br><mark style=\"background-color:#20c997\" class=\"has-inline-color\">\ud83d\udd5a<\/mark>\u00a0<strong>11:00 AM\u201312:00 PM | Ballroom E<\/strong><br><strong>Accelerating GFD RTL Verification: A Lightweight Host-to-GFD Framework<\/strong><br><em>Presented by Wade Chen<\/em><br>See how Siemens\u2019 lightweight framework simplifies GFD verification by bypassing full-fabric simulation.<br> <br><mark style=\"background-color:#20c997\" class=\"has-inline-color\">\ud83d\udd5b<\/mark>\u00a0<strong>12:10\u20131:15 PM | Ballroom D<\/strong><br><strong>Navigating the Chiplet Revolution<\/strong><br><strong>Mastering UCIe 2.0: Overcoming Fabric Management Hurdles for Chiplet Integration<\/strong><br><em>Presented by Prashant Dixit<\/em> &amp; Ujjwai Negi<br>Learn how to manage complex SiP topologies and ensure protocol interoperability using UVM and reusable test environments.<br> <br><strong>Versatile Verification Framework for Multi-Protocol UCIe Design<\/strong><br><em>Presented by Himani Kaushik<\/em><br>Discover a flexible adapter architecture that integrates diverse protocols over UCIe for streamlined system-level verification.<br>  <br><strong>UCIe Chiplet Ecosystem: Interoperable Testbench for Multi-Vendor IP Integration<\/strong>\u00a0<br><em>Presented by Prashant Dixit<\/em><br>Explore a simulation-based interoperability program that accelerates UCIe adoption through early collaboration.<br> <br><mark style=\"background-color:#20c997\" class=\"has-inline-color\">\ud83d\udd50<\/mark>\u00a0<strong>1:25\u20132:30 PM | Ballroom B<\/strong><br><strong>CXL Verification: A Comprehensive Guide<\/strong><br><strong>A Comprehensive Verification Guide for Extended Meta Data<\/strong>\u00a0<br><em>Presented by PJ<\/em> Wang<br>Understand how to verify CXL 3.1\u2019s Extended Meta Data with protocol checkers and error injection.<br>  <br><strong>Enhancing Security in CXL: IDE and TSP Verification<\/strong>\u00a0<br><em>Presented by PJ Wang &amp; Wade Chen (on behalf of Heetashi Arora)<\/em><br>Dive into verification of CXL IDE and TSPs, including coherence, encryption, and access control scenarios.<br> <br><mark style=\"background-color:#20c997\" class=\"has-inline-color\">\ud83d\udd50<\/mark>\u00a0<strong>1:25\u20132:30 PM | Ballroom C<\/strong><br><strong>Evolving UALink and UEC as the Gold Standard for Accelerator Connectivity in AI<\/strong><br><em>Presented by Pankaj Goel<\/em><br>Learn how UALink and UEC deliver scalable, low-latency interconnects for AI workloads using existing PHY infrastructure.<\/li>\n<\/ul>\n\n\n\n<p>We\u2019re excited to connect with fellow innovators, engineers, and industry leaders at FMS 2025.  Whether you&#8217;re attending our sessions or stopping by Booth #1140, we look forward to sharing the latest technical advancements in verification IP, system-level validation, and memory and interconnect technologies.  Let\u2019s explore how Siemens EDA can help you accelerate innovation, ensure interoperability, and build the future of memory and storage\u2014together.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>We\u2019re excited to connect with fellow innovators, engineers, and industry leaders at FMS 2025.  Whether you&#8217;re attending our sessions or stopping by Booth #1140, we look forward to sharing the latest technical advancements in verification IP, system-level validation, and memory and interconnect technologies. <\/p>\n","protected":false},"author":71541,"featured_media":19455,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[5,1634,1,10,983],"tags":[1636,1635,506,906,718,1601,787],"industry":[32,35,54,1564,53,38,37],"product":[1593,205,206],"coauthors":[920],"class_list":["post-19426","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-events","category-avery-vip","category-news","category-tips-tricks","category-uvm","tag-ai-interconnects","tag-avery-vip","tag-functional-verification","tag-nvme","tag-simulation","tag-ucie","tag-uvm","industry-aerospace-defense","industry-avionics-defense-electronics","industry-consumer-industrial-electronics","industry-electronic-design-automation","industry-electronics-semiconductors","industry-land-systems","industry-space-systems","product-avery","product-questa","product-questa-verification-ip"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2025\/07\/FMS-Blog-1-scaled.png","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/19426","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71541"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=19426"}],"version-history":[{"count":4,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/19426\/revisions"}],"predecessor-version":[{"id":19451,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/19426\/revisions\/19451"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media\/19455"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=19426"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=19426"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=19426"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=19426"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=19426"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=19426"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}