{"id":19265,"date":"2025-01-31T16:58:58","date_gmt":"2025-01-31T21:58:58","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/?p=19265"},"modified":"2026-03-27T08:53:10","modified_gmt":"2026-03-27T12:53:10","slug":"accellera-sessions-at-dvcon-u-s-2025","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2025\/01\/31\/accellera-sessions-at-dvcon-u-s-2025\/","title":{"rendered":"Accellera Sessions at DVCon U.S. 2025"},"content":{"rendered":"<div class=\"wp-block-image\">\n<figure class=\"alignright size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"1000\" height=\"693\" src=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2025\/01\/DVCon-U.S.-2025-Logo-1.png\" alt=\"\" class=\"wp-image-19269\" style=\"aspect-ratio:1;width:155px;height:auto\" srcset=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2025\/01\/DVCon-U.S.-2025-Logo-1.png 1000w, https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2025\/01\/DVCon-U.S.-2025-Logo-1-600x416.png 600w, https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2025\/01\/DVCon-U.S.-2025-Logo-1-768x532.png 768w, https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2025\/01\/DVCon-U.S.-2025-Logo-1-900x624.png 900w\" sizes=\"auto, (max-width: 1000px) 100vw, 1000px\" \/><\/figure><\/div>\n\n\n<p>As one of Accellera&#8217;s Global Sponsors, Siemens EDA is happy to help shape the Accellera sessions at DVCon U.S and promote its important work on standards.\u00a0 For 2025 there will be five Accellera workshops, three on Monday and two on Thursday.\u00a0 I can\u2019t recall a time when Accellera has had this many sessions covering its expansive work.\u00a0 Two of the workshop sessions come from Accellera initiated standards that are now IEEE standards.<\/p>\n\n\n\n<p>I hope you will be able to join us at DVCon U.S. which runs 24-27 February 2025, at the DoubleTree in San Jose, CA.&nbsp; The working group leaders have planned insightful presentations with information you can apply to you daily work.&nbsp; The Monday luncheon for DVCon U.S. attendees will feature a general update on the latest Accellera work underway and planned, along with the presentation of the prestigious Accellera Technical Excellence Award and an overview of the emerging UVM-MS 1.0 standard by its working group chair, Tom Fitzpatrick.<\/p>\n\n\n\n<p>The list below is the five Accellera sponsored workshops.&nbsp; (Paid <a href=\"https:\/\/dvcon.org\/\" target=\"_blank\" rel=\"noopener\">DVCon U.S. 2025<\/a> registration is required to attend.)<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><a href=\"https:\/\/dvcon.org\/introduction-of-ieee-1801-2024-upf-4-0-improvements-for-the-specification-and-verification-of-low-power-intent\" target=\"_blank\" rel=\"noopener\"><strong>Introduction of IEEE 1801-2024 (UPF 4.0)<\/strong><\/a><br>Monday, February 24 | 9:00-10:30am<br>This workshop will explore the key advancements in the IEEE 1801-2024 (UPF 4.0) standard, designed to address the growing complexity of modern low-power architectures. Attendees will gain insights into the new methodologies for verification, implementation, and reuse of power intent specifications that are critical for flexible IP design, analog-digital interfaces, and state retention modeling.<br><\/li>\n\n\n\n<li><a href=\"https:\/\/dvcon.org\/moving-forward-with-ieee-1800-2-uvm-practical-insights-and-the-benefits-of-migration\" target=\"_blank\" rel=\"noopener\"><strong>Moving Forward with IEEE 1800.2 UVM: Practical Insights and the Benefits of Migration<\/strong><\/a><br>Monday, February 24 |<strong> <\/strong>11:00-12:30pm<br>This workshop highlights the latest enhancements in the IEEE 1800.2 UVM standard, as introduced in Accellera&#8217;s reference implementation (2020.3.1). It offers practical guidance for verification engineers, focusing on performance improvements, functional updates, and strategies for a smooth migration from UVM 1.2.<br><\/li>\n\n\n\n<li><strong><a href=\"https:\/\/dvcon.org\/pss-comes-of-age-runtime-behavioral-coverage-methodology-and-more\" target=\"_blank\" rel=\"noopener\">PSS Comes of Age: Runtime Behavioral Coverage, Methodology and More<\/a> <\/strong><br>Monday, February 24 | 3:30-5:00<br>This workshop will dive into the key advancements in the Portable Stimulus Standard (PSS) 3.0 and ongoing efforts by the working group, highlighting the language&#8217;s evolution and maturity. Attendees will gain a deeper understanding of PSS 3.0\u2019s capabilities and the tools available to streamline portable stimulus test creation and implementation.<br><\/li>\n\n\n\n<li><strong><a href=\"https:\/\/dvcon.org\/ip-xact-workshop-at-dvcon-us-2025\" target=\"_blank\" rel=\"noopener\">SoC development automation using IP-XACT 1685-2022 standard<\/a> <\/strong><br>Thursday, February 27 | 9:00-10:30<br>This workshop explores the complexities of the SoC development process and highlights how the IEEE IP-XACT 1685-2022 standard streamlines workflows, fosters standardization, and enables automation. Attendees will gain insights into optimizing SoC development by standardizing processes and integrating automation with IP-XACT.<br><\/li>\n\n\n\n<li><a href=\"https:\/\/dvcon.org\/cdc-rdc-interchange-format-standard\" target=\"_blank\" rel=\"noopener\"><strong>CDC\/RDC Interchange Format Standard<\/strong><\/a><br>Thursday, February 27 | 11:00-12:30<br>This workshop highlights the critical role of Clock Domain Crossing and Reset Domain Crossing (RDC) analysis in modern SoC development, addressing challenges posed by increasing design complexity and diverse verification tool ecosystems. Attendees will learn how standardization can enhance quality and efficiency in CDC-RDC analysis for advanced SoC designs.<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>As one of Accellera&#8217;s Global Sponsors, Siemens EDA is happy to help shape the Accellera sessions at DVCon U.S and&#8230;<\/p>\n","protected":false},"author":71541,"featured_media":19273,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[5,1,982,10,983],"tags":[375,442,506,558,1033,732,751,787],"industry":[1564,53],"product":[1593,205,206,1091],"coauthors":[920],"class_list":["post-19265","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-events","category-news","category-systemverilog","category-tips-tricks","category-uvm","tag-cdc","tag-dvcon","tag-functional-verification","tag-ip-xact","tag-rdc","tag-standards","tag-systemverilog","tag-uvm","industry-electronic-design-automation","industry-electronics-semiconductors","product-avery","product-questa","product-questa-verification-ip","product-questa-verification-iq"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2025\/01\/DVCon-On-Stage-Pick.jpg","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/19265","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71541"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=19265"}],"version-history":[{"count":4,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/19265\/revisions"}],"predecessor-version":[{"id":19274,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/19265\/revisions\/19274"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media\/19273"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=19265"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=19265"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=19265"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=19265"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=19265"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=19265"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}