{"id":19246,"date":"2025-02-14T17:29:53","date_gmt":"2025-02-14T22:29:53","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/?p=19246"},"modified":"2026-03-27T08:53:26","modified_gmt":"2026-03-27T12:53:26","slug":"got-coverage","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2025\/02\/14\/got-coverage\/","title":{"rendered":"Got Coverage?"},"content":{"rendered":"\n

Welcome to 2025. What happened?! “Coverage” in August in Yosemite backpacking has a different meaning. In August? Snow? Lots of coverage. Got Coverage? <\/p>\n\n\n\n

But, nevermind – what about YOUR coverage!? You didn’t get enough coverage collected. But just maybe you have a bunch of 0’s and 1’s. You’re late with your coverage, but your old school 0’s and 1’s are going to save the day.<\/p>\n\n\n\n

\"Test
Test vector results – 0’s and 1’s, but I didn’t collect coverage! Yet.<\/figcaption><\/figure>\n\n\n\n

What to do to get Coverage?<\/h2>\n\n\n\n

We can build a coverage collector. We can build a set of coverage models and extract coverage from the 0’s and 1’s. And not just functional coverage.<\/p>\n\n\n\n

\"Coverage<\/figure>\n\n\n\n

If we missed you at DVCON Taiwan 2024<\/a> in September, then you might want to check out our paper<\/a> and slides<\/a>, because that’s exactly what we describe – a way to feed in a file full of 0’s and 1’s and collect coverage.<\/p>\n\n\n\n

The idea is that we’ll read those 0’s and 1’s and assign those bits to “variables” in a SIMULATED environment. The 0’s and 1’s could be from simulation, prototyping, tester results or some other external model. We’ll read them and collect coverage in that SIMULATED environment – it is NOT a re-simulation of the design. It is a SIMULATION built to collect coverage – that’s it.<\/p>\n\n\n\n

\"Coverage
Coverage Report with Block, FSM and Expression Coverage<\/figcaption><\/figure>\n\n\n\n

Those 0’s and 1’s are the values that we want to “measure”. For example, suppose you have a 4 bit value and your coverage is simple – “did all values occur at any time during the simulation?”<\/em> That’s a simple covergroup to write.<\/p>\n\n\n\n

Easy. Our technique covers that.<\/p>\n\n\n\n

If your coverage is more complicated that’s ok. You might need to cover that 4 bit value during all 7 of the state transistions – a cross coverage.<\/p>\n\n\n\n

Easy.<\/p>\n\n\n\n

In addition to functional coverage there are ways to collect FSM coverage and some simple expression coverage and even simple block coverage.<\/p>\n\n\n\n

\"Coverage
Coverage Rollups<\/figcaption><\/figure>\n\n\n\n

This technique can’t give you full coverage across your whole chip, but it can give you focused coverage on some important values. You can cover module instance ports, or registers, or memory locations – whatever got logged in the 0’s and 1’s text file. The file also doesn’t have to be a text file. Whatever kind of file it is, you need to supply a reader for it and be able to get access to the values at a given time.<\/p>\n\n\n\n

Happy 2025! We hope you have a great 2025, and you get that coverage collected.<\/p>\n\n\n\n

See you at DVCON US 2025<\/a>. I’ll be at the Siemens booth, ready to talk about coverage, UVM, debug or anything verification at all. Maybe even Yosemite backpacking. Young Lakes. Half Dome. Clouds Rest. We can talk driver tracing and why debug and coverage is more important than ever. Come see Questa and Visualizer in action. Or we can talk ultra-light backpacking…<\/p>\n\n\n\n

Thanks<\/p>\n\n\n\n

rich<\/p>\n\n\n\n

<\/p>\n","protected":false},"excerpt":{"rendered":"

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