{"id":18411,"date":"2023-06-14T10:37:11","date_gmt":"2023-06-14T14:37:11","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/?p=18411"},"modified":"2026-03-27T08:51:42","modified_gmt":"2026-03-27T12:51:42","slug":"siemens-eda-at-the-60th-dac","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2023\/06\/14\/siemens-eda-at-the-60th-dac\/","title":{"rendered":"Siemens EDA at the 60th DAC"},"content":{"rendered":"\n

Please mark your calendars for the highly anticipated 60th anniversary Design Automation Conference (DAC). The 60th DAC will take place at the Moscone Center West from July 9th to July 13th, 2023. As a proud member of the DAC executive committee for the past seven years, I am honored to inform you that we have meticulously curated an exceptional technical program for this milestone event.<\/p>\n\n\n\n

Established in 1964, DAC stands as the most enduring and extensive gathering focused on research and technology in the design and automation of electronic chips and systems. This conference holds a distinguished reputation for attracting participants from every facet of the system design and development ecosystem, including academia, research, government, and industry. The event’s significance stems from the harmonious fusion of a robust Research Track, an Engineering Track, and a concurrent exhibition featuring industry vendors.<\/p>\n\n\n\n

The DAC 2023 technical program has achieved an unprecedented number of submissions for both the Research Track and Engineering Track. Our Technical Program Committee diligently reviewed 1,156 research manuscripts, ultimately accepting 263 for presentation and publication. This corresponds to an acceptance rate of 22.7 percent. Furthermore, the committee evaluated 269 Engineering Track submissions, selecting 71 for presentation, resulting in an acceptance rate of 26.4 percent.<\/p>\n\n\n\n

In celebration of the 60th DAC, I am delighted to announce the return of Siemens as a Platinum exhibitor, occupying booth #2521. Notably, Siemens boasts an impressive presence in the technical program, with 46 active participants. In this blog post, I will highlight several key Siemens events within the DAC program.<\/p>\n\n\n\n

Visionary Talks:<\/strong> As part of the 60th DAC commemoration, the Executive Committee has decided to reintroduce Visionary Talks, scheduled each morning prior to the Keynote address. These talks will be delivered by eminent industry experts. Our inaugural Visionary Talk will be presented by Joe Sawicki, Executive Vice President of Integrated Circuits and Electronic Design Automation at Siemens EDA. Taking place on Monday, July 10th at 9:00 am, Joe’s talk titled “Systems 2030 \u2013 What’s Needed to Succeed in the Next Decade of Design without Resorting to Human Cloning” will delve into the past, present, and future of complex semiconductor systems design.<\/p>\n\n\n\n

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DAC Pavilion Panel: <\/strong>On Monday, July 10th at 10:15 am, Tony Hemmelgarn, President and CEO of Siemens Digital Industries Software, will participate in a panel discussion titled “Best of Both Worlds \u2013 Bridging the Gap between EDA, System, and Manufacturing.” This panel, featuring prominent software companies, will explore a long-anticipated phenomenon: the convergence of business, market, and technical aspects of Engineering Software (EDA and “industrial” software). These convergences are increasingly evident in the companies’ product and acquisition strategies.<\/p>\n\n\n\n

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Finally, I eagerly anticipate the opportunity to meet you at the esteemed 60th DAC celebration party, scheduled for Tuesday, July 11th of this year.<\/p>\n\n\n\n

For reference, below you will find a comprehensive listing of Siemens EDA’s technical involvement in this year’s DAC program:<\/p>\n\n\n\n

DAC Pavilion Panel<\/td>Design Considerations and Tradeoffs for 2.5D Chiplet Solutions<\/a><\/td><\/tr>
DAC Pavilion Panel<\/td>Best of Both Worlds \u2013 Bridging the Gap between EDA, System and Manufacturing<\/a><\/td><\/tr>
Embedded Systems and Software<\/td>Designing Effective Autonomous Systems and Digital Twins<\/a><\/td><\/tr>
Engineering Track Poster<\/td>A Data Analytics Based Approach for Reducing Clock Tree Power at RTL<\/a><\/td><\/tr>
Engineering Track Poster<\/td>A Statistical approach to identify wasted power consumption in combinational clusters<\/a><\/td><\/tr>
Engineering Track Poster<\/td>Advanced transceiver components for robust handling of signal noise and loss<\/a><\/td><\/tr>
Engineering Track Poster<\/td>An Efficient and Spice Aligned Method for Complex IO’s Behavioral Model Generation and Verification<\/a><\/td><\/tr>
Engineering Track Poster<\/td>An efficient methodology to verify floating point matrix multiplication<\/a><\/td><\/tr>
Engineering Track Poster<\/td>Bridging the Gap Between Neural Network Exploration and Hardware Implementation<\/a><\/td><\/tr>
Engineering Track Poster<\/td>Deep learning Platform for FSM-Based HLS<\/a><\/td><\/tr>
Engineering Track Poster<\/td>Design and Verification of AXI4 Master for ASIC using High Level Synthesis in C++<\/a><\/td><\/tr>
Engineering Track: Back-End Design<\/td>A Novel Solution for 3nm\/4nm and Below LVS Challenges: Local Layout Effects Extraction QA in LVS Rule Deck<\/a><\/td><\/tr>
Engineering Track: Back-End Design<\/td>Packaging and Manufacturing Technologies save the day!<\/a><\/td><\/tr>
Engineering Track: Front-End Design<\/td>Crossing the RISC-V customization barrier with formal<\/a><\/td><\/tr>
Engineering Track: Front-End Design<\/td>Design for Verification – Case Reopened<\/a><\/td><\/tr>
Engineering Track: Front-End Design<\/td>Full SoC power analysis and estimation with end-user software early in the design cycle<\/a><\/td><\/tr>
Engineering Track: Front-End Design<\/td>Dragging Debug into a New Era<\/a><\/td><\/tr>
Engineering Track: Front-End Design<\/td>The Next Frontiers in the Front End<\/a><\/td><\/tr>
Engineering Track: IP<\/td>Comprehensive Validation Solution for Silicon IP&Library<\/a><\/td><\/tr>
Engineering Track: IP<\/td>ML-based High Sigma Verification Methodology: SVS Methodology<\/a><\/td><\/tr>
Research Manuscript<\/td>G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators<\/a><\/td><\/tr>
Research Manuscript<\/td>Everything, EveryPLACE, All at Once!<\/a><\/td><\/tr>
Research Panel<\/td>Achieving Verifiable Autonomy: Is Design Automation the Golden Key?<\/a><\/td><\/tr>
RISC-V Zone<\/td>Creating Domain Specific Accelerators for RISC-V Designs with Siemens EDA<\/a><\/td><\/tr>
RISC-V Zone<\/td>Removing the Risk from RISC-V using the RISC-V Trace Standard<\/a><\/td><\/tr>
Transformative Technologies Theater<\/td>Simplifying Success in the Cloud<\/a><\/td><\/tr>
Transformative Technologies Theater<\/td>The Good, Bad and Cloudy<\/a><\/td><\/tr>
Visionary Talk<\/td>Systems 2030 \u2013 What\u2019s Needed to Succeed in the Next Decade of Design without Resorting to Human Cloning<\/a><\/td><\/tr><\/tbody><\/table><\/figure>\n","protected":false},"excerpt":{"rendered":"

Please mark your calendars for the highly anticipated 60th anniversary Design Automation Conference (DAC). The 60th DAC will take place…<\/p>\n","protected":false},"author":71592,"featured_media":18417,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[409,430,452,658],"industry":[32,39,45,53],"product":[],"coauthors":[967],"class_list":["post-18411","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news","tag-dac","tag-design-automation-conference","tag-eda","tag-questa","industry-aerospace-defense","industry-automotive-transportation","industry-consumer-products-retail","industry-electronics-semiconductors"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2023\/06\/DAC_936443-22_2023_LogoUpdate_tag.png","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/18411","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71592"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=18411"}],"version-history":[{"count":4,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/18411\/revisions"}],"predecessor-version":[{"id":18421,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/18411\/revisions\/18421"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media\/18417"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=18411"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=18411"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=18411"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=18411"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=18411"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=18411"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}