{"id":1819,"date":"2011-01-28T08:16:06","date_gmt":"2011-01-28T15:16:06","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=1819"},"modified":"2026-03-27T08:44:21","modified_gmt":"2026-03-27T12:44:21","slug":"accellera-approves-new-co-emulation-standard","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2011\/01\/28\/accellera-approves-new-co-emulation-standard\/","title":{"rendered":"Accellera Approves New Co-Emulation Standard"},"content":{"rendered":"<p><a href=\"http:\/\/www.accellera.org\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" style=\"padding-left: 0px;padding-right: 0px;float: right;padding-top: 0px\" src=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2011\/01\/image.png\" alt=\"image\" width=\"148\" height=\"66\" align=\"right\" border=\"0\" \/><\/a><\/p>\n<h3>Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity<\/h3>\n<p>The Accellera <a href=\"http:\/\/www.accellera.org\/activities\/itc\" target=\"_blank\" rel=\"noopener\">Interface Technical Subcommittee<\/a> (ITC) completed version 2.1 of the standard used to interface software and hardware-based verification technology.\u00a0 With SCE-MI, models can be developed for simulation to run in an emulation environment and visa versa.<\/p>\n<p>The major addition to SCE-MI 2.1 is support for a subset of the IEEE Std 1800\u2122 (<a href=\"http:\/\/www.svug.org\" target=\"_blank\" rel=\"noopener\">SystemVerilog<\/a>) Direct Programming Interface (DPI) that permits a streaming, variable length messaging system to be built on top of it to reduce the number of synchronizations that would otherwise be required by alternate methods.<\/p>\n<p>The standard is available <a title=\"Accellera SCE-MI 2.1 Standard\" href=\"http:\/\/www.accellera.org\/activities\/itc\/SCE_MI_v21-110112-final.pdf\" target=\"_blank\" rel=\"noopener noreferrer\">here<\/a> free of charge from Accellera.<\/p>\n<p><strong>What does this mean to the verification professional? <\/strong><\/p>\n<p>Dr. van der Schoot has published four sessions on <a href=\"https:\/\/verificationacademy.com\/courses\/systemverilog-testbench-acceleration\" target=\"_blank\" rel=\"noopener\">SystemVerilog Testbench Acceleration<\/a> at the <a href=\"https:\/\/verificationacademy.com\/\" target=\"_blank\" rel=\"noopener\">Verification Academy<\/a> that give an excellent overview of the benefits of this technology.\u00a0 Dr. van der Schoot shows how the prevalent verification methodologies (OVM and UVM) can see dramatic improvements when this technology is applied.<\/p>\n<table border=\"0\" width=\"399\" cellspacing=\"0\" cellpadding=\"2\">\n<tbody>\n<tr>\n<td valign=\"top\" width=\"36\"><\/td>\n<td valign=\"top\" width=\"361\"><strong>Verification Academy Session<\/strong><\/td>\n<\/tr>\n<tr>\n<td valign=\"top\" width=\"36\"><\/td>\n<td valign=\"top\" width=\"361\"><a href=\"https:\/\/verificationacademy.com\/sessions\/hw-assisted-testbench-acceleration\" target=\"_blank\" rel=\"noopener\">Introduction to Hardware Assisted Testbench Acceleration<\/a><\/td>\n<\/tr>\n<tr>\n<td valign=\"top\" width=\"36\"><\/td>\n<td valign=\"top\" width=\"361\"><a href=\"https:\/\/verificationacademy.com\/sessions\/testbench-acceleration-depicted\" target=\"_blank\" rel=\"noopener\">Testbench Acceleration Depicted<\/a><\/td>\n<\/tr>\n<tr>\n<td valign=\"top\" width=\"36\"><\/td>\n<td valign=\"top\" width=\"361\"><a href=\"https:\/\/verificationacademy.com\/sessions\/modeling-for-acceleration\" target=\"_blank\" rel=\"noopener\">Modeling for Acceleration<\/a><\/td>\n<\/tr>\n<tr>\n<td valign=\"top\" width=\"36\"><\/td>\n<td valign=\"top\" width=\"361\"><a href=\"https:\/\/verificationacademy.com\/sessions\/testbench-acceleration-flow\" target=\"_blank\" rel=\"noopener\">Testbench Acceleration Flow<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>How is Co-Emulation Used in Practice?<\/strong><\/p>\n<figure style=\"width: 147px\" class=\"wp-caption alignleft\"><a href=\"https:\/\/blogs.mentor.com\/verificationhorizons\/files\/2011\/01\/edsfair-2011.jpg\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" style=\"padding-left: 0px;padding-right: 0px;padding-top: 0px;border: 0pt none\" src=\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2011\/01\/edsfair-2011-thumb.jpg\" alt=\"EDSFair 2011\" width=\"147\" height=\"176\" align=\"left\" border=\"0\" \/><\/a><figcaption class=\"wp-caption-text\">EDSFair 2011<\/figcaption><\/figure>\n<p>The technology is also deployed in a working verification flow by Mentor Graphics.\u00a0 At EDSFair 2011 in Japan this week, users could see Co-Emulation in action.<\/p>\n<p>This technology has allowed verification runs using the prevalent methodologies, OVM and UVM, to operate easily up to 400x\u00a0 faster when emulation technology is used to accelerate verification as <a href=\"http:\/\/www.mentor.com\/products\/fv\/news\/veloce-ovm-driven-verification\" target=\"_blank\" rel=\"noopener\">previously announced<\/a>.<\/p>\n<p>While EDSFair is over, verification professionals will have another opportunity to see this technology in action at the <a href=\"http:\/\/www.dvcon.org\/\" target=\"_blank\" rel=\"noopener\">DVCon 2011<\/a> exhibition.\u00a0 Dr. van der Schoot also has a paper at DVCon, <em><a href=\"http:\/\/dvcon.org\/events\/eventdetails.aspx?id=121-5\" target=\"_blank\" rel=\"noopener\">Off To The Races With Your Accelerated SystemVerilog Testbench<\/a><\/em>, that he will present to explore details on how this standards technology is being applied in real life.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the&#8230;<\/p>\n","protected":false},"author":71541,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[326,442,454,623,701,732,751,787],"industry":[],"product":[],"coauthors":[],"class_list":["post-1819","post","type-post","status-publish","format-standard","hentry","category-news","tag-accellera","tag-dvcon","tag-edsfair","tag-ovm","tag-sce-mi","tag-standards","tag-systemverilog","tag-uvm"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/1819","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71541"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=1819"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/1819\/revisions"}],"predecessor-version":[{"id":14644,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/1819\/revisions\/14644"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=1819"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=1819"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=1819"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=1819"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=1819"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=1819"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}