Hi Everyone,<\/p>\n
Just wanted to let you know that the latest edition of our Verification Horizons newsletter is available here<\/a>. I\u2019ll be blogging about some of the articles individually a bit later, but for now you can get an overview of the contents from reading my editor\u2019s note. In addition to getting a taste of the articles, you\u2019ll also learn how my daughter\u2019s 10th birthday party was like an engineering project.<\/em><\/em><\/p>\n Here\u2019s the Table of Contents:<\/p>\n Page 6…Survey Says: Verification Planning<\/a> Page 8…Firmware Verification Using SystemVerilog OVM<\/a> Page 14…A SystemVerilog Configurable Coverage Model in an OVM setup<\/a> Page 25…Advanced Techniques for AXI Bus Fabric Verification<\/a> Page 34…Converting Module-Based Verification Environments to Class-Based Using SystemVerilog OOP<\/a> Partners\u2019 Corner
by Harry Foster, Chief Verification Scientist Design Verification Technology,
Mentor Graphics Corporation<\/p>\n
by Ranga Kadambi, Eric Eu, and Sudheer Arey, Infineon Singapore
Mark Glasser and Christoph Suehnel, Mentor Graphics Corporation<\/p>\n
by Parag Goel, and Sakshi Bajaj, Applied Micro
with Pushkar Naik, Applied Micro
and Ashish Kumar, Mentor Graphics Corporation<\/p>\n
by Alain Gonier and Jay O\u2019Donnell, Mentor Graphics Corporation<\/p>\n
by Amit Tanwar, Mentor Graphics Corporation<\/p>\n
<\/strong>Page 38…Verifying a CoFluent SystemC IP Model from a SystemVerilog UVM Testbench in Mentor Graphics Questa<\/a>
by Laurent Isenegger, J\u00e9r\u00f4me Lemaitre and Wander Oliveira Ces\u00e1rio, CoFluent Design<\/p>\n