{"id":17976,"date":"2022-12-26T22:05:17","date_gmt":"2022-12-27T03:05:17","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/?p=17976"},"modified":"2026-03-27T08:50:36","modified_gmt":"2026-03-27T12:50:36","slug":"strongpart-10-the-2022-wilson-research-group-functional-verification-study-strong","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2022\/12\/26\/strongpart-10-the-2022-wilson-research-group-functional-verification-study-strong\/","title":{"rendered":"Part 10: The 2022 Wilson Research Group Functional Verification Study"},"content":{"rendered":"\n

IC\/ASIC Language and Library Adoption Trends<\/strong><\/h2>\n\n\n\n

This blog is a continuation of a series of blogs related to the 2022 Wilson Research Group Functional Verification Study<\/a>. In my previous blog<\/a>, I examined IC\/ASIC project verification technology adoption trends. In this blog I plan to discuss various IC\/ASIC language and library adoption trends.<\/p>\n\n\n\n

Figure 10-1 shows the aggregated adoption trends for languages used to create RTL designs across all market segments and all regions of the world. We see continual interest in SystemVerilog for RTL creation.<\/p>\n\n\n\n

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Figure 10-1. IC\/ASIC Languages Used for RTL Design<\/strong><\/figcaption><\/figure>\n\n\n\n

In Figure 10-2, we show the adoption trends for languages to build testbenches. It is not uncommon for IC\/ASIC projects to use multiple languages when constructing their testbenches, which is why the percentage adoption sums to more than 100 percent. This practice of adopting multiple languages is often due to legacy code as well as purchased verification IP written in a different language.<\/p>\n\n\n\n

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Figure 10-2. IC\/ASIC Languages Used for  Verification (Testbenches)<\/strong><\/figcaption><\/figure>\n\n\n\n

In the 2022 data, we see an increase in adoption of C\/C++ for testbench development. In addition, we show the adoption levels for the Accellera Portable Test and Stimulus Standard (PSS). Finally, in 2022, we explicitly asked about the adoption of Python for testbench development.<\/p>\n\n\n\n

The adoption trends for various methodology standards are shown in Figure 10-3. We found that the Accellera UVM is currently the predominant standard that has been adopted to create IC\/ASIC testbenches. Also, in 2022 we tracked Python-based methodologies, such as cocotb<\/em>.<\/p>\n\n\n\n

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Figure 10-3. IC\/ASIC Methodologies and Testbench Base-Class Libraries<\/strong><\/figcaption><\/figure>\n\n\n\n

Finally, IC\/ASIC project adoption trends for various assertion language standards are shown in Figure 10-4. SystemVerilog Assertions (SVA) is the predominant assertion language in use today. Similar to languages used to build testbenches, it is not unusual to find IC\/ ASIC projects create their RTL in VHDL and then create their assertions using SVA.<\/p>\n\n\n\n

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Figure 10-4. IC\/ASIC Assertion Language Adoption<\/strong><\/figcaption><\/figure>\n\n\n\n

In my next blog I plan to present the IC\/ASIC design and verification power trends.<\/p>\n\n\n\n

Quick links to the 2022 Wilson Research Group Study results<\/strong><\/p>\n\n\n\n