Writing Simple Code<\/h2>\n\n\n\n
It’s really a paper on writing simple, easy to understand models and libraries as opposed to building a register package – although the examples operate as small register packages.<\/p>\n\n\n\n
I’ll share a simple register modeling package and share a small example as we cruise through the ideas and concepts.<\/p>\n\n\n\n The UVM Register package is well used, and well loved – clocking in at about 20,000 lines of code in total. The package discussed in the paper does not assume to be as complete as the UVM Register package – but is it complete enough? I’d love to hear your thoughts in Munich.<\/p>\n\n\n\n I’m a fan of registers, but many (most?) registers cannot just be randomized or stomped through with marching ones. Some can. But could you imagine setting registers to random values in the control chip for the wood chipper that the tree guys use? Wood chippers are scary enough already.<\/p>\n\n\n\n Instead, I think register tests “know what the registers can do” – they are aware. Or at least register tests embody relationships between registers (regA has to be non-zero, when regB[3] is 1). These kinds of relationships can be captured in tests or constraints for example.<\/p>\n\n\n\n Sometimes a useful register testbench just monitors the addresses, and maps the addresses into register names for easier debug. <\/p>\n\n\n\n In any case, a register model is a useful thing. But does it have to be so big?<\/p>\n\n\n\n You were getting ready to ask – “What about the register-to-bus layering”? Simple. A sequence does the work. You write code to go back and forth between the register layer and the bus protocol layer. But not much code. You can change format. You can issue many transactions. It’s just code. And small.<\/p>\n\n\n\n But now I’m getting ahead of the story. More details and discussion at the show.<\/p>\n\n\n\n Create functionally interesting registers like a status register with a READ-ONLY field named ‘active_tr’. The bit-fields are described with a struct. The behavior of this register is “regular” – nothing fancy, except that the the field ‘active_tr’ is READ-ONLY. It cannot be written. So the write() routine is implemented as such.<\/p>\n\n\n\n Simple.<\/p>\n\n\n\n![\"DVCON](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2022\/11\/image-1-1024x680.png\")
Register-To-Bus Layering<\/h2>\n\n\n\n
class <\/strong>REGISTERtoBUS_rw_sequence extends <\/strong>uvm_sequence#(bus_transaction);\n `uvm_object_utils(REGISTERtoBUS_rw_sequence)\n\n bit <\/strong>all_done;\n\n task <\/strong>body();\n `uvm_info(get_type_name(), \"...running\", UVM_MEDIUM)\n all_done = 0;\n wait <\/strong>(all_done == 1);\n endtask\n<\/strong>\n task <\/strong>start_reg_item(register_transaction register_tr);\n bus_transaction bus_tr;\n \/\/ Translate to BUS\n bus_tr = new<\/strong>(\"bus_tr\");\n bus_tr.rw = register_tr.rw;\n bus_tr.addr = register_tr.addr;\n bus_tr.data = register_tr.data;\n start_item(bus_tr);\n register_tr.bus_tr = bus_tr; \/\/ Save it for later.\n \/\/ Translate back to register\n endtask<\/strong>\n\n task <\/strong>finish_reg_item(register_transaction register_tr);\n bus_transaction bus_tr;\n \/\/ Translate to BUS\n $cast(bus_tr, register_tr.bus_tr);\n bus_tr.rw = register_tr.rw;\n bus_tr.addr = register_tr.addr;\n bus_tr.data = register_tr.data;\n finish_item(bus_tr);\n register_tr.data = bus_tr.data;\n \/\/ Translate back to register\n endtask<\/strong>\nendclass<\/strong><\/code><\/pre>\n\n\n\nA Register<\/h2>\n\n\n\n
typedef struct packed <\/strong>{\n reg <\/strong>[1:0] status;\n reg <\/strong>[7:0] error_count;\n reg <\/strong>[4:0] active_tr; \/\/ READ-ONLY<\/em>\n} csr_t;\n\nclass <\/strong>csr_RO_active_tr extends <\/strong>register#(csr_t);\r\n function void <\/strong>write(T v); \r\n value.status = v.status;\r\n value.error_count = v.error_count;\r\n endfunction\r<\/strong>\nendclass\r<\/strong><\/code><\/pre>\n\n\n\n