{"id":17786,"date":"2022-10-30T17:39:44","date_gmt":"2022-10-30T21:39:44","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/?p=17786"},"modified":"2026-03-27T08:50:25","modified_gmt":"2026-03-27T12:50:25","slug":"part-3-the-2022-wilson-research-group-functional-verification-study","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2022\/10\/30\/part-3-the-2022-wilson-research-group-functional-verification-study\/","title":{"rendered":"Part 3: The 2022 Wilson Research Group Functional Verification Study"},"content":{"rendered":"\n

This blog is a continuation of a series of blogs related to the 2022 Wilson Research Group Functional Verification Study<\/a>.  In my previous blog<\/a>, I presented the findings from our new study related to how successful FPGA projects are in terms of verification effectiveness. In this blog I focus on FPGA verification effort trends.<\/p>\n\n\n\n

FPGA Verification Effort Trends<\/strong><\/h2>\n\n\n\n

Directly asking study participants how much effort they spend in verification will not work. The reason is that it\u2019s hard to find a paper or article on verification that doesn\u2019t start with the phrase: \u201cSeventy percent of a project\u2019s effort is spent in verification\u2026\u201d In other words, the industry is already biased to respond with this effort value. Yet, there are really no creditable references to quantify this value.<\/p>\n\n\n\n

I don\u2019t believe that there is a simple answer to the question, \u201cHow much effort was spent on verification in your last project?\u201d In fact, I believe that it is necessary to look at multiple data points derived from multiple questions to truly get a sense of effort spent in verification. And that\u2019s what we did in our functional verification study.<\/p>\n\n\n\n

Percentage of Project Time Spent in Verification<\/strong><\/h2>\n\n\n\n

To try to assess the effort spent in verification, let\u2019s begin by looking at one data point, which is the total project time spent in verification, as shown in Fig. 3-1. You can see two extremes in this graph. In general, projects that spend very little time in verification are typically working on designs with a good deal of existing pre-verified design IP, which is integrated to create a new product. On the other extreme, projects that spend a significant amount of time in verification often have a high percentage of newly developed design IP that must be verified.<\/p>\n\n\n\n

\"\"
Fig. 3-1. Percentage of FPGA project time spent in verification<\/figcaption><\/figure>\n\n\n\n

Overall, we found a slight decline in a project time spent in FPGA verification 2022, which is somewhat of a surprise due to growing complexity.<\/p>\n\n\n\n

Peak Number of Design and Verification Engineers<\/strong><\/h2>\n\n\n\n

Perhaps one of the biggest challenges today is to control cost and engineering headcount, which means identifying FPGA design and verification solutions that increase productivity. To illustrate the need for productivity improvement, we discuss the trend in terms of increasing engineering headcount. Fig. 3-2 shows the mean peak number of FPGA engineers working on a project.<\/p>\n\n\n\n

\"\"
Fig. 3-2. Mean Peak Number of FPGA Engineers Working on a Project<\/figcaption><\/figure>\n\n\n\n

While, on average, the demand for FPGA design engineers increased by 18% between 2012 and 2022, the demand for FPGA verification engineers increased at 38%. It is worth noting that during the period 2007 through 2014, the ASIC market went through similar growth demands related to verification engineers to address growing ASIC verification complexity.<\/p>\n\n\n\n

In my next blog I focus on the time that FPGA design and verification engineers spend in various task.<\/p>\n\n\n\n

Quick links to the 2022 Wilson Research Group Study results<\/strong><\/p>\n\n\n\n