{"id":17663,"date":"2022-10-16T15:41:38","date_gmt":"2022-10-16T19:41:38","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/?p=17663"},"modified":"2026-03-27T08:50:22","modified_gmt":"2026-03-27T12:50:22","slug":"part-1-the-2020-wilson-research-group-functional-verification-study-2","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2022\/10\/16\/part-1-the-2020-wilson-research-group-functional-verification-study-2\/","title":{"rendered":"Part 1: The 2022 Wilson Research Group Functional Verification Study"},"content":{"rendered":"\n

In my previous blog, I introduced the 2022 Wilson Research Group Functional Verification Study (click here<\/a>). The objective of my previous blog was to provide an overview on our large, worldwide industry study. The key findings from this study will be presented in a set of upcoming blogs.<\/p>\n\n\n\n

In this blog, I present trends related to various aspects of FPGA design to illustrate growing design complexity.<\/p>\n\n\n\n

The Global FPGA Semiconductor Market<\/h2>\n\n\n\n

The 2021 global semiconductor market was valued at $552.5 billion after experiencing a 24 percent growth over 2020. The FPGA portion of the semiconductor market was valued at about $5.3 billion in 2021. The FPGA semiconductor market is expected to reach a value of $9.3 billion by 2030, growing at a compounded annual growth rate (CAGR) of 6.5 percent during this forecast period. The growth in this market is being driven by new and expanding end-user applications related to data center computing, networking, and storage, as well as communication.<\/p>\n\n\n\n

Historically, FPGAs have offered two primary advantages over ASICs. First, due to their low NRE, FPGAs are generally more cost effective than IC\/ASICs for lowvolume production. Second, FPGAs\u2019 rapid prototyping capabilities and flexibility can reduce the development schedule since a majority of the verification and validation cycles have traditionally been performed in the lab. More recently, FPGAs offer advantages related to performance for certain accelerated applications by exploiting hardware parallelism (e.g., AI Neural Networks).<\/p>\n\n\n\n

The IC\/ASIC market in the mid- to late-2000 timeframe underwent growing pains to address increased verification complexity. Similarly, we find today\u2019s FPGA market is being forced to address growing verification complexity. With the increased capacity and capability of today\u2019s complex FPGAs and the emergence of high-performance SoC programmable FPGAs (e.g., Xilinx Zynq\u00ae UltraSCALE+, Intel\u00ae Stratix\u00ae, and Microsemi SmartFusion\u00ae), traditional lab-based approaches to FPGA verification and validation are becoming less effective. Later in this blog series, we plan to quantify the ineffectiveness of today\u2019s FPGA verification processes in terms of nontrivial bug escapes into production.<\/p>\n\n\n\n

Obviously, both design and verification complexity increase the multiple embedded processes in a single SoC. In our 2022 study we found that 43 percent of FPGA design projects are working on designs that contain two or more embedded processors, while 4 percent of today\u2019s designs include eight or more embedded processors. SoC class designs add a new layer of verification complexity to the verification process that did not exist with traditional non-SoC class designs due to hardware and software interactions, new coherency architectures, and the emergence of complex network on-a-chip interconnect.<\/p>\n\n\n\n

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Fig. 1-1. Number of embedded processor cores<\/figcaption><\/figure>\n\n\n\n

Our 2020 study, for the first time, tracked the number of FPGA projects that have incorporated a RISC-V processor in their design, which was 23 percent, and we didn\u2019t see any significant change in our 2022 study. However, in 2020 we also started tracking the number of FPGA projects that have incorporated some type of AI accelerator processor (e.g., TPU, etc.), which was 19 percent. This grew to 23 percent in 2022.<\/p>\n\n\n\n

Asynchronous Clock Domains<\/h2>\n\n\n\n

In Fig. 1-2, we see that 92% of designs being implemented as FPGAs contain two or more asynchronous clock domains. Verifying requirements associated with multiple asynchronous clock domains has increased both the verification workload and complexity. For example, a class of metastability bugs cannot be demonstrated on an RTL model using simulation. To simulate these issues requires a gate-level model with timing, which is often not available until later stages in the design flow. However, static clock-domain crossing (CDC) verification tools have emerged and are being adopted to help identify clock domain issues directly on an RTL model at earlier stages in the design flow.<\/p>\n\n\n\n

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Fig. 1-2. Number of asynchronous clock domains<\/figcaption><\/figure>\n\n\n\n

Security Features<\/h2>\n\n\n\n

Today we find that 49 percent of FPGA projects add security features to their designs. Examples of security features include security assurance hardware modules (e.g., a security controller) that are designed to safely hold sensitive data, such as encryption keys, digital right management (DRM) keys, passwords, and biometrics reference data. These security features add requirements and complexity to the verification process.<\/p>\n\n\n\n

Safety Features<\/h2>\n\n\n\n

Another example of increasing requirements contributing to complexity relates to safety-critical designs. In 2022 we found that 42 percent of all FPGA projects are working under one of multiple safety-critical development process standards or guidelines.<\/p>\n\n\n\n

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Fig. 1-3. Safety critical development standard used on FPGA projects<\/figcaption><\/figure>\n\n\n\n

The key takeaway from this blog is that FPGA designs are growing in complexity, which impacts verification effort and effectiveness.<\/p>\n\n\n\n

In my next blog, I\u2019ll focus on verification effectiveness trends related to FPGA designs.<\/p>\n\n\n\n

Quick links to the 2022 Wilson Research Group Study results<\/strong><\/p>\n\n\n\n