![\"IEC](\"https:\/\/blogs.mentor.com\/verificationhorizons\/files\/2010\/10\/iec2010.jpg\")
<\/a> The IEC\u2019s 47th General Assembly meeting opened on October 11th in Seattle, WA USA.\u00a0 Plans had been put in place for about 2,500 delegates but that number was exceeded by nearly 25% with more than 3,100 people registered.\u00a0 Three days before the start of the meeting the Technical Committee 93, which addresses all the design automation standards held seven working group meetings from Friday-Sunday.\u00a0 On Monday the group reported out conclusions of all the committee\u2019s working groups.<\/p>\nThe TC 93 addresses a broad spectrum of standards for the design automation of electronic devices ranging from printed circuit boards and systems to semiconductor devices and systems.\u00a0 From that broad swath of interests, two dual-logo candidates germane to language-based design flows were on the agenda for consideration by the IEC Standards Management Board (SMB).<\/p>\n Specifically, IEEE Std 1076-2008 and IEEE Std 1800-2009 were approved by the SMB at the start of the meeting series on 11 October 2010 as dual-logo standards.\u00a0 For those who purchase their standards from the IEC or their national standards bodies, the VHDL standard is known as IEC 61691-1-1 Ed. 2.0 (2010) and the SystemVerilog standard is known as IEC 62530 Ed. 2.0 (2010).\u00a0 The content between the IEEE and IEC are the same with the exception of the cover page of the standard, which will carry both the IEEE and IEC logo.\u00a0 Different countries have different rules and laws to recognize standards.\u00a0 The IEC plays a key role to bridge these differences to promote efficient and effective global use of VHDL, Verilog, SystemVerilog, SystemC and more.<\/p>\n","protected":false},"excerpt":{"rendered":" United States Plays Host in Seattle, WA The IEC\u2019s 47th General Assembly meeting opened on October 11th in Seattle, WA…<\/p>\n","protected":false},"author":71541,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[303,307,309,313,440,525,528,732,749,751,754,831,833,848],"industry":[],"product":[],"coauthors":[],"class_list":["post-1710","post","type-post","status-publish","format-standard","hentry","category-news","tag-303","tag-307","tag-309","tag-313","tag-dual-logo","tag-iec","tag-ieee","tag-standards","tag-systemc","tag-systemverilog","tag-tc93","tag-verilog","tag-vhdl","tag-wg2"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/1710","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71541"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=1710"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/1710\/revisions"}],"predecessor-version":[{"id":14646,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/1710\/revisions\/14646"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=1710"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=1710"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=1710"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=1710"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=1710"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=1710"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}![\"TC93](\"https:\/\/blogs.mentor.com\/verificationhorizons\/files\/2010\/10\/tc93wg2.jpg\")
<\/a> Working Group 2 manages the process to promote dual-logo standards development between the IEEE and IEC for design languages and may be of particular interest to VHDL, Verilog, SystemVerilog and SystemC users.\u00a0 In addition to the responsibility to manage design language dual-logo standards, WG 2 has maintenance responsibility for IBIS, the I\/O Buffer Information Specification. IBIS 4.2<\/a> is on the work plan for standardization.\u00a0 The Japanese National Committee\u2019s technical report from JEITA on their Bird\u2019s eye View of Design Language (BVDL) was also submitted as an official submission.<\/p>\n