Retargeting FPGAs would be easy if designers used only RTL. In that case, we’d retarget resynthesizing in a different vendor’s tool flow. However, FPGA designers usually take advantage of vendor\u2013supplied design IP by dragging and dropping blocks into a schematic and connecting them with custom RTL.<\/p>\n\n\n\n
Design IP tied to a specific FPGA vendor or a specific FPGA model means that we cannot simply resynthesize a design. We must create a new version of the design using a new library of IP and then connect our custom RTL to it. How do you verify that the two designs are identical?<\/p>\n\n\n\n
FPGA retargeting verification goal<\/h2>\n\n\n\n
<\/p>\n\n\n\n
- Ensure that the netlist matches the original RTL.<\/li>
- Modify the RTL using the new chip’s design IP.<\/li>
- Ensure that the new RTL matches the new netlist.<\/li><\/ul>\n\n\n\n
![\"FPGA](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2022\/02\/fpga-retargeting-1024x506.png\")
FPGA retargeting verification<\/figcaption><\/figure>\n\n\n\n One approach to solving this problem is to assume that the RTL and the netlists match and run the RTL against a simulation testbench. This assumes that the testbench has complete coverage and that its stimulus addresses all corner cases. Simulation is a good verification solution, but it doesn’t provide gap\u2013free assurance that both FPGAs match.<\/p>\n\n\n\n
FPGA retargeting verification webinar<\/h2>\n\n\n\n
Another approach to verifying a retargeted design is to prove that the netlists are identical to the RTL and then prove that RTL for each FPGA delivers identical functionality.<\/p>\n\n\n\n
The webinar Overcoming Today\u2019s Verification, Supply Chain, and Legacy Technology Challenge Associated with FPGA\u2013based Designs<\/em> will show you how to deliver gap\u2013free FPGA retargeting verification.<\/p>\n\n\n\n
The webinar will outline the verification solutions and retargeting solutions that deliver a solution to deal with FPGA supply chain issues and to extend the life of legacy designs powered by old or obsolete FPGAs. A workflow and methodology will be provided for each scenario, along with real\u2013world case studies.<\/p>\n\n\n\n
What You Will Learn:<\/strong><\/p>\n\n\n\n
- The challenges facing FPGA\u2013based designers<\/li>
- Mitigating FPGA supply chain shortages and legacy design dilemma<\/li>
- The verification strategies to ensure FPGA\u2013based designs have zero bug escapes<\/li><\/ul>\n\n\n\n
Who Should Attend:<\/strong><\/p>\n\n\n\n