{"id":16507,"date":"2021-09-09T15:45:40","date_gmt":"2021-09-09T19:45:40","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/?p=16507"},"modified":"2026-03-27T08:47:49","modified_gmt":"2026-03-27T12:47:49","slug":"python-and-the-uvm","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2021\/09\/09\/python-and-the-uvm\/","title":{"rendered":"Python and the UVM"},"content":{"rendered":"\n

In our previous two posts in this series on Python as a verification language, we examined Python coroutines<\/a> and using coroutines to create cocotb<\/strong> bus functional models<\/a>. Now we are going to look at the next step, the Universal Verification Methodology (UVM) implemented in Python.<\/p>\n\n\n\n

The UVM is completely described in the IEEE 1800.2-2020 standard. The standard describes the UVM’s classes and functions and also describes some of the detail of how it has been implemented in SystemVerilog.<\/p>\n\n\n\n

I use the IEEE UVM standard to create pyuvm<\/strong>, a clean-sheet reimplementation of the UVM from the standard. Refactoring the UVM in Python allowed me to simplify the code and take advantage of Python features such as multiple inheritance that made, for example, the _imp<\/code> classes unnecessary.<\/p>\n\n\n\n

The initial release, pyuvm<\/strong> 1.0 implemented the UVM using Python threads. However, once cocotb<\/strong> released coroutine versions of Python Queues, it became clear that a cocotb<\/strong>-based pyuvm<\/strong> would be much easier to use. We’ll examine pyuvm<\/strong> 2.0 in this blog post.<\/p>\n\n\n\n

Focusing on differences<\/h1>\n\n\n\n

This article assumes that the reader is familiar with the SystemVerilog version of the UVM. It will use an example testbench for the TinyALU as a path through a UVM testbench written in Python.<\/p>\n\n\n\n

Python, with its lack of typing and dynamic nature, is easier to write than SystemVerilog, and so I refactored much of the UVM to take advantage of Python’s features. We’ll see these changes as we work through the testbench.<\/p>\n\n\n\n

The cococtb<\/strong> test<\/h1>\n\n\n\n

We’ll start a the top of the testbench with the coroutine that we’ve tagged with the @cocotb.test()<\/code> decorator:<\/p>\n\n\n\n

import<\/span> cocotb\nfrom<\/span> pyuvm import<\/span> *<\/span>\n\n@cocotb.test<\/span>()\nasync<\/span> def<\/span> test_alu<\/span>(dut<\/span>):\n    bfm =<\/span> TinyAluBfm(dut) \n    ConfigDB().set(None<\/span>, \"*\"<\/span>, \"BFM\"<\/span>, bfm)\n    await<\/span> bfm.startup_bfms()\n    await<\/span> uvm_root().run_test(\"AluTest\"<\/span>)<\/code><\/pre>\n\n\n\n
The first thing to note is the way we imported pyuvm<\/strong>. When we work in SystemVerilog we write import uvm_pkg::*<\/code> which makes all the UVM classes and functions available in our code without referencing the package. We’re doing the same here in Python.<\/p>\n\n\n\n
ConfigDB().set(None, \"*\", \"BFM\", bfm)<\/code><\/p>\n\n\n\n
Storing an item in the config_db<\/code> in the SystemVerilog UVM entails using a long incantation with various types and static function calls. Under the hood the uvm_config_db<\/code> interfaces is built upon the uvm_resource_db<\/code> which has a complicated way of storing a variety of data types in a database.<\/p>\n\n\n\n
pyuvm<\/strong> does away with all this. Instead of static function calls, it provides a singleton that stores data in the configuration database using the same hierarchy-based control as the SystemVerilog version.<\/p>\n\n\n\n
The ConfigDB()<\/code> call looks like an instantiation, but it is actually returning the handle to a singleton. Python doesn’t require an explicit get()<\/code> static method to implement singletons.<\/p>\n\n\n\n
The result is a call to ConfigDB().set()<\/code> without the incantations needed to store values of a specific type. Any object can be stored anywhere in the pyuvm<\/strong> ConfigDB()<\/code>.<\/p>\n\n\n\n
The next thing we do in the test is launch the BFMs using the bfm.startup_bfms()<\/code> coroutine. The coroutines forks off the BFM coroutines as we saw in the bus functional model blog post.<\/a>  <\/p>\n\n\n\n
We see in the last line that the UVM task run_test()<\/code> is now a coroutine. We get a handle to the uvm_root()<\/code> singleton and await run_test()<\/code>, passing the name of the test so the factory can create it.  We’ll see the AluTest class defined below.<\/p>\n\n\n\n
Awaiting Tasks<\/h2>\n\n\n\n
The await<\/code> call to run_test()<\/code> demonstrates a nice feature of Python: we call tasks and functions differently.<\/p>\n\n\n\n
In SystemVerilog, we call a function that returns void<\/code> and a task the same way. There is nothing to indicate that the call could consume time. Python requires that all time-consuming calls be done using await<\/code>.<\/p>\n\n\n\n
The UVM test: AluTest<\/h1>\n\n\n\n
Our call to run_test()<\/code> above took the string AluTest<\/code> as an argument, which means we should look at AluTest<\/code> for more differences between Python UVM and SystemVerilog UVM:<\/p>\n\n\n\n
class<\/span> AluTest<\/span>(uvm_test<\/span>):\n    def<\/span> build_phase<\/span>(self<\/span>):\n        self<\/span>.env =<\/span> AluEnv.create(\"env\"<\/span>, self<\/span>)\n\n    async<\/span> def<\/span> run_phase<\/span>(self<\/span>):\n        self<\/span>.raise_objection()\n        seqr =<\/span> ConfigDB().get(self<\/span>, \"\"<\/span>, \"SEQR\"<\/span>)\n        bfm =<\/span> ConfigDB().get(self<\/span>, \"\"<\/span>, \"BFM\"<\/span>)\n        seq =<\/span> AluSeq(\"seq\"<\/span>)\n        await<\/span> seq.start(seqr)\n        await<\/span> ClockCycles(bfm.dut.clk, 50<\/span>)  # to do last transaction\n<\/span>        self<\/span>.drop_objection()\n\n    def<\/span> end_of_elaboration_phase<\/span>(self<\/span>):\n        self<\/span>.set_logging_level_hier(logging.DEBUG<\/span>)<\/code><\/pre>\n\n\n\n
The first thing to notice is that Alutest<\/code> extends uvm_test<\/code>. Though Python style prefers camel casing for classes, pyuvm<\/strong> preserves all the class names from the standard. The exception is when, as with ConfigDB()<\/code> the feature has been completely refactored.<\/p>\n\n\n\n
Notice that we don’t have the \\`uvm_component_utils()<\/code> macro or its equivalent in the code. This is because pyuvm<\/strong> automatically registers all classes that extend uvm_void<\/code> in the factory.<\/p>\n\n\n\n
The build_phase()<\/code> function<\/h2>\n\n\n\n
The build_phase()<\/code> function demonstrates that pyvum<\/strong> implements what the UVM spec calls the common_phases<\/code>. The lack of a uvm_phase phase<\/code> argument in build_phase()<\/code> shows that pyuvm<\/strong> refactors phasing. It only<\/em> implements the common phases and there is no mechanism to create custom phases, as this feature is rarely used.<\/p>\n\n\n\n
The build_phase()<\/code> function creates an environment named self.env<\/code> using the factory. The call to the factory is much simpler than it is in SystemVerilog. We don’t have the heroic string of static function calls and variables in a SystemVerilog UVM factory incantation. Instead, create<\/code> is simply a static method in all classes that extend uvm_object<\/code>. The factory implements all the override functionality found in the SystemVerilog UVM.<\/p>\n\n\n\n
The run_phase()<\/code> coroutine<\/h2>\n\n\n\n
In SystemVerilog UVM the run_phase()<\/code> is the only phase implemented as a time-consuming task. The same is true in pyuvm<\/strong>, as run_phase()<\/code> is implemented as a coroutine.<\/p>\n\n\n\n
This means that you must use the async<\/code> keyword to define the run_phase()<\/code>.<\/p>\n\n\n\n
There is no phase<\/code> argument, so the raise_objection()<\/code> and drop_objection()<\/code> functions are methods in uvm_component<\/code>. The UVM will run until the every raise_objection<\/code> has been matched by a drop_objection<\/code>.<\/p>\n\n\n\n
The run_phase()<\/code> creates a sequence of type AluSeq<\/code> and gets the sequencer out of the ConfigDB()<\/code>. Then it uses await<\/code> to kick off the start()<\/code> task in the sequence.<\/p>\n\n\n\n
The end_of_elaboration_phase()<\/code> function<\/h2>\n\n\n\n
The end_of_elaboration_phase()<\/code> function runs after the UVM has built the testbench hierarchy and connected all the FIFOs. In this example, we use it to set our logging level.<\/p>\n\n\n\n
Notice that pyuvm<\/strong> does not implement the UVM reporting system, as Python provides the logging<\/code> module. Instead, pyuvm<\/strong> leverages logging<\/code> and provides hierarchical functions for us to control logging behavior.<\/p>\n\n\n\n
Summary<\/h1>\n\n\n\n
This blog post introduced pyuvm<\/strong>, a Python implementation of the UVM built upon cocotb<\/strong>. While pyuvm<\/strong> implements all the features we expect from the UVM including the config db and the factory, it refactors elements of the UVM that are easier to use in Python.<\/p>\n\n\n\n
You can see the source code for pyuvm<\/strong> at https:\/\/github.com\/pyuvm\/pyuvm<\/a>.<\/p>\n\n\n\n
You can install pyuvm<\/strong> from pypi.org using pip<\/code>:<\/p>\n\n\n\n
% pip install pyuvm<\/code><\/p>\n\n\n\n
This will also install cocotb<\/strong><\/p>\n\n\n\n
The next blog post in the series will examine logging in more detail, as well as pyuvm<\/strong>‘s implementation of TLM 1.0.<\/p>\n","protected":false},"excerpt":{"rendered":"
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The test starts simply enough. We create a bfm<\/code> object that contains the bus functional models we created in the previous blog post<\/a>. The next line is from pyuvm<\/strong> and demonstrates the simplicity of writing UVM code in Python: we store the BFM in the configuration database.<\/p>\n\n\n\n