{"id":16304,"date":"2021-07-07T12:37:07","date_gmt":"2021-07-07T16:37:07","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/?p=16304"},"modified":"2026-03-27T08:47:01","modified_gmt":"2026-03-27T12:47:01","slug":"qrun-ing-optimized-build-flows-in-questasim","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2021\/07\/07\/qrun-ing-optimized-build-flows-in-questasim\/","title":{"rendered":"Qrun-ing Optimized Build Flows in Questasim"},"content":{"rendered":"\n<h1 class=\"wp-block-heading\"><strong>Qrun-ing with Questasim<\/strong><\/h1>\n\n\n\n<p>For Questasim users, qrun will be a welcome surprise. Admittedly, I\u2019ve never been a huge fan of the 3-step Questasim flow of vlog, vopt and vsim. On one hand it does give you intimate access to the simulator that customers can use to optimize their usage. On the flip side, that level of control requires a lot of knowledge and understanding that presents challenges to new users.<\/p>\n\n\n\n<p>My personal list of complaints with the 3-step flow is that it has three steps! I want one step and that\u2019s what qrun gives me. Another pet peeve was always vsim running the GUI by default instead of batch mode. For me, running with the GUI has always been the exception so having batch as the default mode for qrun makes my life easier. Tied for third place are a few other little quirks, like needing to specify a name for the optimized image out of vopt, the obligatory two command vsim tcl input of -do \u201crun -all; quit\u201d, routing verilog and VHDL source files to the right compiler executable (i.e. vlog or vcom) and some switch redundancy between steps.<\/p>\n\n\n\n<p>In short, qrun eliminates a lot of the manual command line construction and linkage required in the 3-step flow. Effectively, it makes qrun the friendly front-end I always wished Questasim had. For that reason, new users want to start with qrun instead of the 3-step flow. No question.<\/p>\n\n\n\n<p>For long-time users, qrun is a streamlined version of the 3-step flow so I recommend making the transition. Even for power users pushing Questasim to the limits, the added ease-of-use will be compelling enough to change.<\/p>\n\n\n\n<h1 class=\"wp-block-heading\"><strong>Qrun-ing an Optimized Build Flow<\/strong><\/h1>\n\n\n\n<p>Let\u2019s get back to the discussion around build flows and the <a href=\"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2021\/05\/17\/expediting-simulation-turn-around-time-with-incremental-build-flows\/\">incremental build options<\/a> I introduced a few weeks ago. In <a href=\"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2021\/05\/17\/expediting-simulation-turn-around-time-with-incremental-build-flows\/\">that post<\/a> we had five options &#8211; lump sum, partitioned compile, parallel compile, pre-optimized design units (PDU) and elaboration flow. For those same five options, let\u2019s get to the details of how they\u2019re done with qrun.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Lump Sum Build<\/strong><\/h2>\n\n\n\n<p>The lump sum build isn\u2019t exactly notable, but it does give me a chance to highlight the simplicity of the qrun interface relative to the 3-step flow. Assuming a single design file list and testbench file list, just feed them into qrun as-is; that does all of compile, optimize and simulate without any other input required.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">qrun -f tb_files.f -f design_files.f<\/pre>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Partitioned Compile<\/strong><\/h2>\n\n\n\n<p>Breaking a design and testbench into multiple libraries is something that our customers do regularly. For that, the old 3-step flow would require vlib and vlog\/vcom for each library. For qrun, we need similar instructions but less information with the -makelib\/-end switches.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">qrun -makelib tb_lib -f tb_files.f -end \\\n     -makelib design_lib -f design_files.f -end<\/pre>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Parallel Compile<\/strong><\/h2>\n\n\n\n<p>Now a big step forward where we can parallelize the compile and distribute it across multiple cores. Adding the -parallel switch to the command line turns on parallel compile. From there, qrun determines dependencies and an optimal number of cores for compilation then launches the jobs to match the dependencies.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">qrun -makelib tb_lib -f tb_files.f -end \\\n     -makelib design_lib -f design_files.f -end \\\n     -parallel<\/pre>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Pre-optimized Design Units (PDUs)<\/strong><\/h2>\n\n\n\n<p>The interface to the PDU flow is similar to the partitioned library compilation. Use the -makepdu\/-end switches to specify the PDU libraries and hierarchies, then qrun optimizes that PDU as an independent entity.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">qrun -makelib tb_lib -f tb_files.f -end \\\n     -makelib design_lib -f design_files.f -end \\\n     -makepdu design_top design_lib.top -L design_lib -end \\\n     -parallel<\/pre>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Elaboration Flow<\/strong><\/h2>\n\n\n\n<p>The elaboration flow is two steps. The first step produces an elaboration file through the addition of the -elab switch. From there, the elab file is used for simulation only in subsequent calls to qrun. The more sims you run, the more the elaboration flow saves you.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted\">qrun -makelib tb_lib -f tb_files.f -end \\\n     -makelib design_lib -f design_files.f -end \\\n     -makepdu design_top design_lib.top -L design_lib -end \\\n     -parallel \\\n     -elab elab.output -do \u201cquit\u201d\nqrun -load_elab elab.output -do \u201crun -all; quit\u201d<\/pre>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Incremental Compile\/Optimize<\/strong><\/h2>\n\n\n\n<p>Another feature of qrun worth mentioning is an incremental compile and optimize. Incremental compile and optimize is integral to the way qrun processes file input. Files are only re-compiled if they change; PDUs are only rebuilt if dependencies change. This is another out-of-the-box convenience upgrade relative to the 3-step flow. Incremental compile is available in the 3-step flow, but with qrun it\u2019s on by default.<\/p>\n\n\n\n<h1 class=\"wp-block-heading\"><strong>Qrun Command to Rule Them All<\/strong><\/h1>\n\n\n\n<p>That\u2019s the end of our qrun crash course. For new Questasim users I\u2019ll reiterate that qrun is where you want to start. Ease-of-use and default options are both improved to the point qrun provides a much stronger first impression than the 3-step flow. For long time users, hopefully I\u2019ve made a compelling case for moving into qrun from the 3-step flow. Not mandatory, but I do think you will find it much friendlier so worth a look.<\/p>\n\n\n\n<p>-neil<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Qrun-ing with Questasim For Questasim users, qrun will be a welcome surprise. Admittedly, I\u2019ve never been a huge fan of&#8230;<\/p>\n","protected":false},"author":72194,"featured_media":16310,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[],"industry":[],"product":[],"coauthors":[939],"class_list":["post-16304","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2021\/07\/part2.png","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/16304","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/72194"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=16304"}],"version-history":[{"count":5,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/16304\/revisions"}],"predecessor-version":[{"id":16309,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/16304\/revisions\/16309"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media\/16310"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=16304"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=16304"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=16304"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=16304"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=16304"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=16304"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}