A lump sum build is the simplest build approach. All the inputs into one bucket; that bucket of stuff compiled into one library; one compiled library produces the optimized simulator input.<\/p>\n\n\n\n At the sub-system level, a lump sum build approach may be all you ever need. From a file server point-of-view, design and testbench infrastructure tend to be well contained so gathering tool inputs like filelists and test or configuration control is straightforward. Team sizes are relatively small at 2-5 people so dependency questions are easy to answer. Most importantly, we\u2019re usually using seconds to measure build times. Back in my verification days I was always hyper-sensitive to long build times. But even for me, lump sum build times were often perfectly acceptable.<\/p>\n\n\n\n Partitioned Compile<\/strong><\/p>\n\n\n\n A lump sum build is handy but it does reach its limit; usually seen by teams that tend toward regular design IP integration and testbench layering. Instead of compiling a single library, smart design and testbench partitioning extends past the architecture to include compiled libraries. Libraries are compiled independently, then collected into one optimized simulation input.<\/p>\n\n\n\n The value of a partitioned compile usually becomes apparent in larger sub-systems. There\u2019s the immediate and obvious impediment of total compile time for a flat list of inputs. Avoiding any part of that can add up to minutes saved on each build. There\u2019s also the engineering effort that goes into building the tool input where a shallow, distributed compile hierarchy helps to localize the knowledge and maintenance effort required.<\/p>\n\n\n\n Parallel Compile<\/strong><\/p>\n\n\n\n With a smart library partitioning strategy, the next natural step to address build turn-around time is parallel compile. The performance value here is pretty easy to quantify: more cores in parallel means shorter build time overall. No picture required!<\/p>\n\n\n\n Pre-optimized Design Units (PDU)<\/strong><\/p>\n\n\n\n The SoC level presents the next significant opportunity for build flow optimization in the form of pre-optimized design units. PDUs extend the idea of individual compiled libraries a step further where large design hierarchies are compiled and <\/em>optimized independently. Those PDUs are then plugged in as-is to become part of the optimized input to the simulator.<\/p>\n\n\n\n PDUs are ideal for large or mature design hierarchies that change infrequently. For example, sub-system teams may drop new RTL on a weekly basis; the SoC verification team then turns the code drop into one or more PDUs. Remaining build cycles are dedicated to the testbench.<\/p>\n\n\n\n Elaboration Flow<\/strong><\/p>\n\n\n\n The final step in an optimized build flow comes via the Questasim elaboration flow. Users create an elaboration file on an initial test run, then specify that file to avoid re-elaboration in subsequent runs.<\/p>\n\n\n\n The elaboration flow is particularly valuable in regressions because elaboration time multiplies across an entire test suite. It\u2019s ideal in cases where your primary test controls rely on run-time decision making; a notable example being the +UVM_TEST plusarg input for UVM test selection. UVM specifically breaks the dependency between test selection and test infrastructure to avoid per test build. As a result, Questasim\u2019s elaboration flow nicely serves performance sensitive UVM test regressions.<\/p>\n\n\n\n Your Optimal Build Flow<\/strong><\/p>\n\n\n\n To summarize, Questasim users have a lot of flexibility when it comes to finding the build flow that\u2019s right for them. Whether you\u2019re verifying a small sub-system as a one-person team or an entire SoC with a much larger team, the combination of compiled library partitioning, PDUs, parallelism and elaboration flow are the tools you need for an optimal build flow and reduced build times.<\/p>\n\n\n\n We\u2019ll leave it there for now. But I\u2019ll be back in a follow-up with more details on how Questasim users use these approaches. Specifically, we\u2019ll see Questasim\u2019s new command line interface – qrun – and how it integrates approaches for your optimal build flow.<\/p>\n\n\n\n -neil<\/p>\n","protected":false},"excerpt":{"rendered":" Rapid simulation turn-around time is critical for high-functioning SoC teams because it enables a tight feedback cycle that teams use…<\/p>\n","protected":false},"author":72194,"featured_media":16161,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[357,724,787,800],"industry":[],"product":[],"coauthors":[939],"class_list":["post-16159","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news","tag-automation","tag-soc-level-verification","tag-uvm","tag-uvm-package"],"featured_image_url":"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2021\/05\/elab.png","_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/16159","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/72194"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=16159"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/16159\/revisions"}],"predecessor-version":[{"id":16160,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/16159\/revisions\/16160"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media\/16161"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=16159"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=16159"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=16159"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=16159"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=16159"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=16159"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}![\"\"\/](\"https:\/\/lh6.googleusercontent.com\/Xb_qozkNJRaxgRSRSR2nmVCDpaxqA8Fo3iHKee1Vu1p8Fk-Qu74DoVEpQj16lbq9sLJl4KVlkU8FJsGnfSDeSyLXH2eBXcQ9jFhuoGAFnTRt_I9dyDnM6375FwndYce_7v17-fbj\")
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