{"id":15643,"date":"2021-01-06T11:40:43","date_gmt":"2021-01-06T16:40:43","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/?p=15643"},"modified":"2026-03-27T08:46:18","modified_gmt":"2026-03-27T12:46:18","slug":"part-8-the-2020-wilson-research-group-functional-verification-study","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2021\/01\/06\/part-8-the-2020-wilson-research-group-functional-verification-study\/","title":{"rendered":"Part 8: The 2020 Wilson Research Group Functional Verification Study"},"content":{"rendered":"\n

IC\/ASIC Resource Trends<\/strong><\/h2>\n\n\n\n

This blog is a continuation of a series of blogs related to the 2020 Wilson Research Group Functional Verification Study<\/a>. In my previous blog<\/a>, I presented trends related to various aspects of design to illustrate growing design complexity. In this blog, I plan to discuss the growing IC\/ASIC project resource trends resulting from growing design complexity.<\/p>\n\n\n\n

Percentage of Project Time Spent in Verification<\/strong><\/h3>\n\n\n\n

Figure 8-1 shows the percentage of total IC\/ASIC project time spent in verification. You can see two extremes in this graph. In general, projects that spend very little time in verification are typically working on designs with a good deal of existing pre-verified design IP, which is integrated to create a new product. On the other extreme, projects that spend a significant amount of time in verification often have a high percentage of newly developed design IP that must be verified.<\/p>\n\n\n\n

\"\"
Figure 8-1. Percentage of IC\/ASIC Project Time Spent in Verification<\/strong><\/figcaption><\/figure>\n\n\n\n

Notice the increase in project times greater than 60 percent for this year\u2019s study. Again, this is a potential indication of growing design and verification complexity.<\/p>\n\n\n\n

Mean Peak Number of Engineers<\/strong><\/h3>\n\n\n\n

Perhaps one of the biggest challenges today is to control cost and engineering headcount, which means identifying IC\/ASIC design and verification solutions that increase productivity. To illustrate the need for productivity improvement, we discuss the trend in terms of increasing engineering headcount. Fig. 8-2 shows the mean peak number of IC\/ASIC engineers working on a project. <\/p>\n\n\n\n

\"\"
Figure 8-2. Mean Number of Peak Engineers per IC\/ASIC Project<\/strong><\/figcaption><\/figure>\n\n\n\n

While, on average, the demand for IC\/ASIC design engineers grew at about a 3 percent CAGR between 2007 and 2020, the demand for IC\/ASIC verification engineers grew at a 6.8 percent CAGR. Today, on average, across all market segments, we find about a one-to-one ratio in terms of mean peak number of verification and design engineers. However, in some market segments, such as processors, it is not unusual to find a 5-to-1 ratio.<\/p>\n\n\n\n

Where Design Engineers Spend Their Time<\/strong><\/h3>\n\n\n\n

But verification engineers are not the only project stakeholders involved in the verification process. Design engineers spend a significant amount of their time in verification too, as shown in fig. 8-3.<\/p>\n\n\n\n

\"\"
Figure 8-3. Where IC\/ASIC Design Engineers Spend Their Time<\/strong><\/figcaption><\/figure>\n\n\n\n

In 2020, design engineers spent on average 53 percent of their time involved in design activities and 47 percent of their time in verification. However, when compared to 2014, the data indicate a trend showing that IC\/ASIC design engineers are now spending slightly less time involved in verification tasks.<\/p>\n\n\n\n

Where Verification Engineers Spend Their Time<\/strong><\/h3>\n\n\n\n

Fig. 8-4 shows where verification engineers spend their time (on average) for various task. Our study found that IC\/ASIC verification engineers spend more of their time debugging than with any other activity. From a management perspective, this can be a significant challenge when planning future projects\u2019 effort and schedule based on previous projects\u2019 data since debugging is unpredictable and varies significantly between projects.<\/p>\n\n\n\n

\"\"
Figure 8-4. Where IC\/ASIC Verification Engineers Spend Their Time<\/strong><\/figcaption><\/figure>\n\n\n\n

In my next blog I plan to discuss various IC\/ASIC verification technology adoption trends.<\/p>\n\n\n\n

Quick links to the 2020 Wilson Research Group Study results<\/strong><\/h3>\n\n\n\n