![\"\"](\"https:\/\/blogs.sw.siemens.com\/wp-content\/uploads\/sites\/54\/2020\/03\/tb_xact_flow.png\")
<\/a><\/p>\n- \n
- Sequencer<\/strong> vs. sequence. That little \u2018r<\/strong>\u2019 confuses a lot of people. If you are new to UVM, just remember:\n
- \n
- A sequencer<\/strong> is basically a smart pipe that carries transactions from the test level to the driver. (Yes, it can do more\u2026)<\/li>\n
- Multiple transactions are called a sequence. A single transaction won’t find many bugs, but a flock of them can be dangerous!<\/li>\n<\/ul>\n<\/li>\n
- Why are multiple transactions put in a task?\n
- \n
- OK, I am generating transactions. Why don\u2019t I just put them into an array?<\/li>\n
- The fourth dimension of your testbench is time! If I just made an array of transaction handles, how do I add delays? If I have two sequences running side by side, into two different interfaces, how do I synchronize them?<\/li>\n
- Each sequence needs to run in the body() task so I can do all this. (Remember, a function can’t have any delays.)<\/li>\n
- What about reactive stimulus? An array of transaction handles is static. What if you want to send in transaction A, check the result, and send in B on success, or C on failure? Or take the value from a read transaction and write that to a new location? This is easy in a SystemVerilog task, but hard with an array of handles.<\/li>\n<\/ul>\n<\/li>\n
- When does my UVM class constructor have one argument vs. two? This is because are two major types of UVM classes.\n
- \n
- Components such as monitors and drivers. These are part of a testbench hierarchy, the boxes shown above.\n
- \n
- A test has an environment, which has an agent, which has a monitor, driver, and sequencer<\/strong>. When you create a component, it needs to know its name and parent. So its new() must have these two arguments.<\/li>\n<\/ul>\n<\/li>\n
- Transactions or sequence items, the orange circles above. These objects are created at the test level, and are sent to an agent. Or created by a monitor and sent to a scoreboard or psychiatrist for analysis. They don\u2019t have a fixed location in the testbench. That\u2019s why their new() only has a single name argument.<\/li>\n<\/ul>\n<\/li>\n
- What does it mean to “start a sequence”?\n
- \n
- A sequence generates transactions. Where do they go? If they are UART transactions, obviously they go to the UART agent. What if there are 4 UARTS in your design? Then your testbench has 4 UART agents. Your test needs to pick one.<\/li>\n
- An agent is just a container for other components. So a sequence needs to connect to a driver. However, what if two sequences both want to send to a single driver. Aha \u2013 you need a smart connection, a sequencer<\/strong>. That is why your test class passes a sequencer<\/strong> handle into the sequence start() task.<\/li>\n
- I prefer to say, “start a sequence with <\/em>a sequencer<\/strong>“, instead of, “start a sequence on <\/em>a sequencer<\/strong>“. A sequencer<\/strong> does not execute a sequence, and virtual sequences usually don’t have a sequencer<\/strong>.<\/li>\n
- OK, that ‘r<\/strong>‘ is getting annoying. You get the picture.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n
Want to see more SystemVerilog and UVM tips? Sign up for my upcoming webinar UVM Coding Guidelines: Tip & Tricks You Probably Didn’t Know<\/a>.<\/p>\n
Enjoy your verification journey!
\nChris Spear
\nhttp:\/\/mentor.com\/training<\/a><\/p>\nAny questions or ideas?\u00a0https:\/\/verificationacademy.com\/content\/uvm-systemverilog-ask-chris-spear<\/a><\/h6>\n","protected":false},"excerpt":{"rendered":"
Or: What I forgot in class When I first learned UVM, there were many things that baffled me. What was…<\/p>\n","protected":false},"author":71586,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[7,1,982,10,983],"tags":[334,382,397,503,515,614,707,708,751,753,757,787],"industry":[],"product":[],"coauthors":[980],"class_list":["post-14020","post","type-post","status-publish","format-standard","hentry","category-learning-resources","category-news","category-systemverilog","category-tips-tricks","category-uvm","tag-agent","tag-class","tag-constructor","tag-function","tag-handle","tag-oop","tag-sequence","tag-sequencer","tag-systemverilog","tag-task","tag-test","tag-uvm"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/14020","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71586"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=14020"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/14020\/revisions"}],"predecessor-version":[{"id":18196,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/14020\/revisions\/18196"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=14020"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=14020"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=14020"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=14020"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=14020"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=14020"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
- I prefer to say, “start a sequence with <\/em>a sequencer<\/strong>“, instead of, “start a sequence on <\/em>a sequencer<\/strong>“. A sequencer<\/strong> does not execute a sequence, and virtual sequences usually don’t have a sequencer<\/strong>.<\/li>\n
- A test has an environment, which has an agent, which has a monitor, driver, and sequencer<\/strong>. When you create a component, it needs to know its name and parent. So its new() must have these two arguments.<\/li>\n<\/ul>\n<\/li>\n
- Components such as monitors and drivers. These are part of a testbench hierarchy, the boxes shown above.\n
- A sequencer<\/strong> is basically a smart pipe that carries transactions from the test level to the driver. (Yes, it can do more\u2026)<\/li>\n