{"id":14016,"date":"2020-03-02T16:00:56","date_gmt":"2020-03-02T23:00:56","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=14016"},"modified":"2026-03-27T08:49:37","modified_gmt":"2026-03-27T12:49:37","slug":"dvconus-edition-of-verification-horizons-is-out","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2020\/03\/02\/dvconus-edition-of-verification-horizons-is-out\/","title":{"rendered":"DVConUS Edition of Verification Horizons is Out!"},"content":{"rendered":"<p>Hi Everyone,<\/p>\n<p>Hello from those of us willing to brave the Coronavirus to be here at DVConUS. I am pleased to announce the the March, 2020 issue of\u00a0<em>Verification Horizons<\/em> is now available. In addition to a discussion about the future of New England Patriots quarterback Tom Brady, you&#8217;ll find a wealth of practical verification information in the great collection of articles in this edition:<\/p>\n<ul>\n<li>Verify Thy Verifyer, from Verifworks &#8211;\u00a0an overview of some useful UVM tricks and pitfalls to avoid,\u00a0but the article also introduces their automated rule checker that helps identify strengths and weaknesses in your UVM code.<\/li>\n<li>AI-Based Sequence Detection from Agnisys &#8211; A fascinating overview of AI for natural language processing, and an introduction to their tool that will auto-generate assertions and sequences from requirements written in a natural language.<\/li>\n<li>Using Questa\u00ae SLEC to Speed Up Verification of Multiple HDL Outputs from Codasip &#8211;\u00a0a case study of how they use Questa\u00ae Sequential Logic Equivalence Checker (SLEC) to compare multiple implementations of a given processor to a fully-verified implementation, reducing many hours of verification down to just minutes.<\/li>\n<li>An Open Data Management\u00a0Tool for Design and Verification from Arastu Systems &#8211; a discussion discussion of the requirements for a tool that will allow effective\u00a0management of Big Data for our verification.<\/li>\n<li>Detecting Scurity Vulnerabilities in a RISC-V\u00ae Based System-on-Chip from Tortuga Logic &#8211; a case study of their experience in winning last year\u2019s Hack@DAC\u00a0contest by successfully detecting and reporting\u00a0security bugs in an RTL RISC-V\u00ae based SoC.<\/li>\n<li>Formal Verification of RISC-V Processors from Axiomise &#8211;\u00a0a good overview\u00a0of common architectural issues you\u2019ll encounter with\u00a0RISC-V, and how a formal tool like Questa\u00a0PropCheck can be used to detect these kinds of bugs early in the design cycle.<\/li>\n<\/ul>\n<p>If you&#8217;re at DVConUS this week, please stop by for an elbow-bump, or just wave.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Hi Everyone, Hello from those of us willing to brave the Coronavirus to be here at DVConUS. I am pleased&#8230;<\/p>\n","protected":false},"author":71936,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[],"industry":[],"product":[],"coauthors":[],"class_list":["post-14016","post","type-post","status-publish","format-standard","hentry","category-news"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/14016","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71936"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=14016"}],"version-history":[{"count":2,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/14016\/revisions"}],"predecessor-version":[{"id":17598,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/14016\/revisions\/17598"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=14016"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=14016"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=14016"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=14016"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=14016"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=14016"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}