{"id":13831,"date":"2019-05-14T16:12:46","date_gmt":"2019-05-14T23:12:46","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=13831"},"modified":"2026-03-27T08:42:09","modified_gmt":"2026-03-27T12:42:09","slug":"mitigating-security-risks-when-designing-with-3rd-party-silicon-ip","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2019\/05\/14\/mitigating-security-risks-when-designing-with-3rd-party-silicon-ip\/","title":{"rendered":"Mitigating Security Risks When Designing with 3rd-Party Silicon IP"},"content":{"rendered":"

<\/a>Accellera DAC Panel to Discuss<\/h3>\n

There is probably not one embedded system that is not built without open source software, 3rd party silicon IP or manufactured far from the design and distribution centers that make and sell these systems.\u00a0 Those who want to secure the design and delivery chain have no standard to use to address this.\u00a0 This has left develop teams to struggle with means to mitigate and address security risks when third party IP and associated components are integrated into today\u2019s modern embedded systems.<\/p>\n

There are many conferences devoted to security related issues and we have all read about Meltdown<\/strong><\/a> and Spectre<\/strong><\/a>, I suspect.\u00a0 There are some security risks which may not have gotten extensive global attention like A2<\/strong><\/a> which is an analog attack exploiting an almost hidden capacitor.\u00a0 The Electronic Design Automation industry has even had exploits documented in conference papers that show how encrypted design and verification IP can be made visible, for which the standards team is now hard at work to address.<\/p>\n

And for embedded systems we have accepted a certain level of risk when it comes to integrating third-party IP into our SoC devices.\u00a0 Modern SoC designs gain productivity leverage when they can be designed with silicon IP that comes from multiple sources, from sources that have expertise in those particular blocks.\u00a0 Who do you use and trust for your memory controllers, protocol interface handlers and the like?\u00a0 In order to build the best SoC, we seek out the highest quality silicon IP to be part of our SoC\u2019s.<\/p>\n

Are these high quality silicon IP\u2019s free of exploits?\u00a0 Have they arrived for integration into your SoC without being tampered?\u00a0 What level of assurance do you have they are safe and clean?\u00a0 You may have the source, but when SoC integrators use the blocks, they are most likely treated as a black-boxes and not heavily vetted for compromise.<\/p>\n

To help address these issues, Accellera\u2019s newest working group, the IP Security Assurance Working Group<\/strong><\/a> was formed.\u00a0 To share more with the design automation and IP community, Accellera is hosting a luncheon on Monday at the 56th Design Automation Conference with a panel of industry experts to address these issues and more.\u00a0 You are invited to attend!<\/p>\n

Accellera DAC IP Security Assurance Luncheon & Panel Event Details<\/h3>\n

Join panelists from Analog Devices, DARPA, Intel and Tortuga Logic for a lively discussion.\u00a0 The luncheon is free for DAC\u00a0 attendees, but registration<\/a> <\/strong>with Accellera is required.<\/p>\n

Monday, June 3rd
\nNoon \u2013 1:30pm
\nRoom N246, Las Vegas Convention Center
\nRegistration and more information: Click Here<\/strong><\/a><\/p>\n

I look forward to seeing you there!<\/p>\n","protected":false},"excerpt":{"rendered":"

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