{"id":13673,"date":"2019-02-19T08:21:58","date_gmt":"2019-02-19T15:21:58","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=13673"},"modified":"2026-03-27T08:42:10","modified_gmt":"2026-03-27T12:42:10","slug":"tom-fitzpatrick-honored-with-accellera-technical-excellence-award","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2019\/02\/19\/tom-fitzpatrick-honored-with-accellera-technical-excellence-award\/","title":{"rendered":"Tom Fitzpatrick Honored with Accellera Technical Excellence Award"},"content":{"rendered":"<h3>Recognized for contributions to Verilog, SystemVerilog, UVM and Portable Stimulus<\/h3>\n<p><a href=\"https:\/\/www.accellera.org\/news\/press-releases\/278-tom-fitzpatrick-to-receive-accellera-systems-initiative-technical-excellence-award\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone\" style=\"margin: 0px 0px 0px 8px;float: right\" title=\"TFitz\" src=\"https:\/\/blogs.mentor.com\/verificationhorizons\/files\/2019\/02\/TFitz.jpg\" alt=\"TFitz\" width=\"160\" height=\"189\" align=\"right\" border=\"0\" \/><\/a>Accellera has selected our own Tom Fitzpatrick as its <a href=\"https:\/\/www.accellera.org\/news\/press-releases\/278-tom-fitzpatrick-to-receive-accellera-systems-initiative-technical-excellence-award\" target=\"_blank\" rel=\"noopener\"><strong>2019 Technical Excellence Award<\/strong><\/a> honoree \u2013 and he joins a select group of distinguished technologist to receive this prestigious recognition.<\/p>\n<p>From all of us at Mentor, we congratulate him on this recognition as it honors his career-long commitment to standards and work to enhance electronic design and verification productivity.\u00a0 Currently, Tom is vice chair of Accellera\u2019s <a href=\"https:\/\/www.accellera.org\/activities\/working-groups\/portable-stimulus\/\" target=\"_blank\" rel=\"noopener\"><strong>Portable Stimulus Working Group<\/strong><\/a> which one of its newest standards.\u00a0 He helped launch the the exploratory activities within Accellera to determine the need and possible market acceptance for the <a href=\"https:\/\/www.accellera.org\/downloads\/standards\/portable-stimulus\" target=\"_blank\" rel=\"noopener\"><strong>Portable Test and Stimulus Standard<\/strong><\/a>.\u00a0 This exploratory work resulted in the formation of the working group for which he is vice chair and highlights his collaboration with peers that resulted in <a href=\"https:\/\/www.accellera.org\/news\/press-releases\/266-accellera-approves-new-portable-test-and-stimulus-standard-quote-sheet\" target=\"_blank\" rel=\"noopener\"><strong>broad industry support<\/strong><\/a> of this new standard.<\/p>\n<p>Tom\u2019s collaboration with his peers has been a hallmark of his work to help create standards and itself is a <em>standard<\/em> by which he is recognized in this honor.\u00a0 Tom started his standards journey with the Verilog language where he eventually held a leadership position in the IEEE 1364 Working Group.\u00a0 He followed this to champion the creation of IEEE 1800 (SystemVerilog) and the Universal Verification Methodology (UVM), now known as IEEE 1800.2.<\/p>\n<p>It is often commented that standards development is much like making sausage: It is often best seen after it is done.\u00a0 But jokes aside, the consensus process to ensure all participants are heard and ideas considered requires patience and an open mind that is fused with finesse to drive standards development forward.\u00a0 Tom has done this well since his early days of Verilog standardization, and has done it with aplomb.<\/p>\n<h3>Award Presented at DVCon U.S. 2019<\/h3>\n<p>Accellera will present Tom with his award at <a href=\"https:\/\/dvcon.org\/\" target=\"_blank\" rel=\"noopener\"><strong>DVCon U.S. 2019<\/strong><\/a> on Monday, February 25th during the Accellera Day luncheon from 12:00 \u2013 1:30pm at the DoubleTree Hotel in San Jose, CA.\u00a0 As a registered conference attendee, you can join him as he accepts his award.\u00a0 You will also be able to catch him during DVCon U.S. exhibit hours in and around the Mentor booth. (<a href=\"https:\/\/dvcon.org\/rates\" target=\"_blank\" rel=\"noopener\"><strong>Exhibit-only passes<\/strong><\/a> are fee-free with an advanced registration.)\u00a0 And if you get a chance, you may want to ask him what standard should come next.<\/p>\n<p>For those who are too far from DVCon U.S., you will continue to see Tom online as the editor of the <strong><a href=\"https:\/\/verificationacademy.com\/verification-horizons\" target=\"_blank\" rel=\"noopener\">Verification Horizons<\/a><\/strong> publication and as one of the subject matter experts at <strong><a href=\"https:\/\/verificationacademy.com\/\" target=\"_blank\" rel=\"noopener\">Verification Academy<\/a><\/strong>.<\/p>\n<p>Congratulations Tom!<\/p>\n<p><a href=\"https:\/\/blogs.mentor.com\/verificationhorizons\/files\/2019\/02\/TFitz-1.jpg\" target=\"_blank\" rel=\"noopener\">\u00a0<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Recognized for contributions to Verilog, SystemVerilog, UVM and Portable Stimulus Accellera has selected our own Tom Fitzpatrick as its 2019&#8230;<\/p>\n","protected":false},"author":71541,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[326,530,533,534,638,652,732,751,756,787,824,831],"industry":[],"product":[],"coauthors":[],"class_list":["post-13673","post","type-post","status-publish","format-standard","hentry","category-news","tag-accellera","tag-ieee-1364","tag-ieee-1800","tag-ieee-1800-2","tag-portable-stimulus","tag-pss","tag-standards","tag-systemverilog","tag-technical-excellence-award","tag-uvm","tag-verification-horizons","tag-verilog"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/13673","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71541"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=13673"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/13673\/revisions"}],"predecessor-version":[{"id":14568,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/13673\/revisions\/14568"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=13673"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=13673"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=13673"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=13673"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=13673"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=13673"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}