{"id":13521,"date":"2019-01-29T08:11:09","date_gmt":"2019-01-29T15:11:09","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=13521"},"modified":"2026-03-27T08:49:48","modified_gmt":"2026-03-27T12:49:48","slug":"part-8-the-2018-wilson-research-group-functional-verification-study","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2019\/01\/29\/part-8-the-2018-wilson-research-group-functional-verification-study\/","title":{"rendered":"Part 8: The 2018 Wilson Research Group Functional Verification Study"},"content":{"rendered":"

IC\/ASIC Resource Trends<\/b><\/h1>\n

This blog is a continuation of a series of blogs related to the 2018 Wilson Research Group Functional Verification Study. \u00a0In my previous blog, I presented trends related to various aspects of design to illustrate growing design complexity. In this blog, I plan to discuss the growing IC\/ASIC project resource trends resulting from growing design complexity.<\/p>\n

Percentage of Project Time Spent in Verification<\/h2>\n

Figure 8-1 shows the percentage of total IC\/ASIC project time spent in verification. As you would expect, the results are all over the spectrum; whereas, some projects spend less time in verification, other projects spend more. The average total project time spent in verification in 2018 was 53 percent, which did not change significantly between 2012 through 2018. This is remarkable considering that designs have grown in terms of size and complexity, yet the overall percentage of project time spent on verification has relatively remained constant.<\/p>\n

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Figure 8-1. Percentage of IC\/ASIC Project Time Spent in Verification<\/b><\/p>\n

Mean Peak Number of Engineers<\/h2>\n

Perhaps one of the biggest challenges in design and verification today is identifying solutions to increase productivity and control engineering headcount. To illustrate the need for productivity improvement, we discuss the trend in terms of increasing engineering headcount. Figure 8-2 shows the mean peak number of engineers working a projects between 2007 and 2018. Again, this is an industry average since some projects have many engineers while other projects have few with differing ratios. You can see that the mean peak number of verification engineers today is just slightly greater than the mean peak number of design engineers. In other words, there are, on average, more verification engineers working on a project than design engineers. This situation has changed significantly since 2007.<\/p>\n

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Figure 8-2. Mean Number of Peak Engineers per IC\/ASIC Project<\/b><\/p>\n

Another way to comprehend the impact of today\u2019s project headcount trends is to calculate the compounded annual growth rate (CAGR) for both design and verification engineers working on projects. Between 2007 and 2014 the industry experienced a 3.8 percent CAGR for design engineers and an impressive 12.6 percent CAGR for verification engineers. Clearly, the double-digit increase in required verification engineers during this period was\u00a0 a major project cost management concern, and is one indicator that the industry under scoped the verification effort during this period. To address growing verification complexity the industry was forced to mature its verification processes. Today, we find that the demand for verification engineers has flattened out between 2014 and 2018. Essentially we have reached a one-to-one ratio in terms of mean peak number of design and verification engineers.<\/p>\n

Where Design Engineers Spend Their Time<\/h2>\n

But verification engineers are not the only project stakeholders involved in the verification process. Design engineers spend a significant amount of their time in verification too, as shown in Figure 8-3. In 2014, design engineers spent on average 47 percent of their time involved in design activities and 53 percent of their time in verification. While in 2018 we found that design engineers spent on average 54 percent of their time involved in design activities and 46 percent of their time in verification.<\/p>\n

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Figure 8-3. Where IC\/ASIC Design Engineers Spend Their Time<\/b><\/p>\n

One factor contributing to the increased percentage of time a design engineer spends in design activities is the growing number of design requirements, as illustrated in Figure 8-4.<\/p>\n

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Figure 8-4. New Layers of Requirements Driving Complexity<\/b><\/p>\n

Where Verification Engineers Spend Their Time<\/h2>\n

Figure 8-5 shows where verification engineers spend their time (on average). Our study found that verification engineers spend more of their time in debugging than any other activity. In fact, we found that the time spent in debugging grew significantly between 2016 (39%) and 2018 (44%).\u00a0From a management perspective, this can be a significant challenge when planning future projects\u2019 effort and schedule based on previous projects\u2019 data since debugging is unpredictable and varies significantly between projects.<\/p>\n

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Figure 8-5. Where IC\/ASIC Verification Engineers Spend Their Time<\/b><\/p>\n

In my next blog, I plan to discuss various IC\/ASIC verification technology adoption trends.<\/p>\n

Quick links to the 2018 Wilson Research Group Study results<\/h2>\n
    \n
  • Prologue: The 2018 Wilson Research Group Functional Verification Study<\/li>\n
  • Understanding and Minimizing Study Bias (2018 Study)<\/li>\n
  • Part 1 \u2013 FPGA Design Trends<\/li>\n
  • Part 2 \u2013 FPGA Verification Effectiveness Trends<\/li>\n
  • Part 3 \u2013 FPGA Verification Effort Trends<\/li>\n
  • Part 4 \u2013 FPGA Verification Effort Trends (Continued)<\/li>\n
  • Part 5 \u2013 FPGA Verification Technology Adoption Trends<\/li>\n
  • Part 6 \u2013 FPGA Verification Language and Library Adoption Trends<\/li>\n
  • Part 7 \u2013 IC\/ASIC Design Trends<\/li>\n
  • Part 8 \u2013 IC\/ASIC Resource Trends<\/li>\n
  • Part 9 \u2013 IC\/ASIC Verification Technology Adoption Trends<\/li>\n
  • Part 10 \u2013 IC\/ASIC Language and Library Adoption Trends<\/li>\n
  • Part 11 \u2013 IC\/ASIC Power Management Trends<\/li>\n
  • Part 12 \u2013 IC\/ASIC Verification Results Trends<\/li>\n
  • Conclusion: The 2018 Wilson Research Group Functional<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"

    IC\/ASIC Resource Trends This blog is a continuation of a series of blogs related to the 2018 Wilson Research Group…<\/p>\n","protected":false},"author":71592,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[506,820,822,827,851],"industry":[],"product":[],"coauthors":[967],"class_list":["post-13521","post","type-post","status-publish","format-standard","hentry","category-news","tag-functional-verification","tag-verification-academy","tag-verification-engineer","tag-verification-methodology","tag-wilson-research-group-functional-verification-study"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/13521","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71592"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=13521"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/13521\/revisions"}],"predecessor-version":[{"id":17612,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/13521\/revisions\/17612"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=13521"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=13521"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=13521"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=13521"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=13521"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=13521"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}