{"id":13464,"date":"2019-01-15T09:44:50","date_gmt":"2019-01-15T16:44:50","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=13464"},"modified":"2026-03-27T08:39:18","modified_gmt":"2026-03-27T12:39:18","slug":"part-6-the-2018-wilson-research-group-functional-verification-study","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2019\/01\/15\/part-6-the-2018-wilson-research-group-functional-verification-study\/","title":{"rendered":"Part 6: The 2018 Wilson Research Group Functional Verification Study"},"content":{"rendered":"

FPGA Language and Library Trends<\/strong><\/h1>\n

This blog is a continuation of a series of blogs related to the 2018 Wilson Research Group Functional Verification Study (click here<\/a>).\u00a0 In my previous blog (click here<\/a>) I discussed FPGA verification techniques and technologies adoption trends, as identified by the 2018 Wilson Research Group study. In this blog, I\u2019ll present FPGA design and verification language adoption trends.<\/p>\n

It is not uncommon for FPGA projects to use multiple languages when constructing their RTL and testbenches. This practice is often due to legacy code as well as purchased IP. Hence, you might note that the percentage adoption for some of the languages that I present sums to more than one hundred percent.<\/p>\n

FPGA RTL Design Language Adoption Trends<\/strong><\/h2>\n

Let\u2019s begin by examining the languages used for FPGA RTL design. Figure 6-1 shows the trends in terms of languages used for design, by comparing the 2012, 2014, 2016, and 2018 Wilson Research Group study, as well as the projected design language adoption trends within the next twelve months. Note that the language adoption is flat or declining for most of the languages used for FPGA RTL design with the exception of Verilog and SystemVerilog.<\/p>\n

Also, it\u2019s important to note that this study focused on languages used for RTL design. We have conducted a few informal studies related to languages used for architectural modeling\u2014and it\u2019s not too big of a surprise that we see increased adoption of C\/C++ and SystemC in that space. However, since those studies have (thus far) been informal and not as rigorously executed as the Wilson Research Group study, I have decided to withhold that data until a more formal study can be executed related to architectural modeling and virtual prototyping.<\/p>\n

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Figure 6-1. Trends in languages used for FPGA design<\/strong><\/p>\n

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VHDL has historically been predominant language used for FPGA RTL design, although it is slowly declining when viewed as a worldwide trend. An important note here is that if you were to filter the results down by a particular market segment or region of the world, you would find different results. For example, if you only look at Europe, you would find that VHDL adoption as an FPGA RTL design language is about 78 percent, while the world average is 62 percent. However, I believe that it is important to examine worldwide trends to get a sense of where the overall industry is moving in the future in terms of design ecosystems.<\/p>\n

FPGA Verification Language Adoption Trends<\/strong><\/h2>\n

Next, let\u2019s look at the languages used to verify FPGA designs (that is, languages used to create simulation testbenches). Figure 6-2 shows the trends in terms of verification languages used to create simulation testbenches by comparing the 2012, 2014, 2016, and 2018 Wilson Research Group study, as well as the projected verification language adoption trends within the next twelve months.<\/p>\n

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Figure 6-2. Trends in languages used in verification to create FPGA simulation testbenches<\/strong><\/p>\n

Historically, VHDL was the predominant language for FPGA testbenches, yet it has leveled off to about 45% adoption, and have seen an increase in SystemVerilog adoption. Today, it is not unusual that the RTL design was created using VHDL, and the testbench was created using SystemVerilog. The increase in \u201cOther\u201d in 2018 is due to the recent adoption of various scripting languages by various FPGA projects (e.g., Python). Finally, the downward trend in VHDL and Verilog adoption in 2016 was probably an anomaly in the study. It is more likely that adoption has only slightly declined or remained flat in 2016.<\/p>\n

FPGA Testbench Methodology Class Library Adoption Trends<\/strong><\/h2>\n

The adoption trends for various base-class library and methodology standards are shown in Fig. 6-3, and we found that the Accellera UVM is currently the predominant standard that has been adopted to create FPGA testbenches worldwide. You might note that we are not showing historical trends for the Open Source VHDL Verification Methodology\u2122 (OSVVM) and the Universal VHDL Verification Methodology (UVVM) since 2018 was the first year we tracked these methodologies.<\/p>\n

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Figure 6-3. FPGA methodology and class library adoption trends<\/strong><\/p>\n

As I previously stated, if you were to filter the results down by a particular market segment or region of the world, you would find different results. For example, we found that worldwide about 17 percent of the study participants have adopted OSVVM while 10 percent of projects have adopted UVVM. Yet, if you filter the results to the specific region of Europe then you will find that 30 percent of the Europe participants have adopted OSVVM while 26 percent have adopted UVVM.<\/p>\n

FPGA Assertion Language and Library Adoption Trends<\/strong><\/h2>\n

Finally, FPGA project adoption trends for various assertion language standards are shown in Fig. 6-4, where SystemVerilog Assertions (SVA) is the predominate language. Similarly to languages used to build testbenches, it is not unusual to find FPGA projects create their RTL in VHDL and then create their assertions using SVA.<\/p>\n

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Figure 6-4. Trends in assertion language and library adoption for FPGA designs<\/strong><\/p>\n

In my next blog (click here<\/a>), I will shift the focus from FPGA trends and start to present the IC\/ASIC findings from the 2018 Wilson Research Group Functional Verification Study.<\/p>\n

Quick links to the 2018 Wilson Research Group Study results<\/h2>\n