{"id":13448,"date":"2019-01-07T08:51:32","date_gmt":"2019-01-07T15:51:32","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=13448"},"modified":"2026-03-27T08:39:16","modified_gmt":"2026-03-27T12:39:16","slug":"part-5-the-2018-wilson-research-group-functional-verification-study","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2019\/01\/07\/part-5-the-2018-wilson-research-group-functional-verification-study\/","title":{"rendered":"Part 5: The 2018 Wilson Research Group Functional Verification Study"},"content":{"rendered":"

This blog is a continuation of a series of blogs related to the 2018 Wilson Research Group Functional Verification Study (click here<\/a>).\u00a0 In my previous blog (click here<\/a>) I discussed verification effort trends specifically focused on where FPGA design and verification engineers spend their time. In this blog I present verification techniques and technologies adoption trends, as identified by the 2018 Wilson Research Group study.<\/p>\n

FPGA Verification Technology Adoption Trends<\/h1>\n

An interesting trend we see in the FPGA space is a continual maturing of its functional verification processes. In fact, we find that the FPGA design space is about where the ASIC\/IC design space was about seven years ago in terms of verification maturity\u2014and it is catching up quickly. A question you might ask is, \u201cWhat is driving this trend?\u201d In Part 1 of this blog series I showed rising design complexity with the adoption of more advanced FPGA designs, as well as multiple embedded processor architectures targeted at FPGA designs. In addition, I\u2019ve presented trend data that showed an increase in total project time and effort spent in verification (Part 3 and Part 4). To address growing verification complexity, we find that many FPGA projects have been forced to mature their verification processes. In this section, we present FPGA trends related to the adoption of various verification techniques, which are fairly standard practice today on most IC\/ASIC projects.<\/p>\n

FPGA Simulation Technique Adoption Trends<\/h2>\n

Fig. 5-1 shows the FPGA project adoption trends for various simulation-based techniques from 2012 through 2018, which include code coverage, functional coverage, assertions, and constrained-random simulation.<\/p>\n

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Figure 5-1. Simulation-based technique adoption trends for FPGA designs<\/b><\/p>\n

FPGA Formal Technology Adoption Trends<\/h2>\n

The adoption trends for formal property checking (e.g., model checking) and automatic formal applications are shown in Fig. 5-2. We found that the adoption of formal property checking on FPGA projects is growing at an impressive 21% CAGR, and the adoption of automatic formal applications is growing at a 29% CAGR. Historically, the formal property checking process has required specialized skills and expertise. However, the recent emergence of automatic formal applications provides narrowly focused solutions and does not require specialized skills for adoption. In general, formal solutions (i.e., formal property checking combined with automatic formal applications) are one of the fastest growing segments in functional verification.<\/p>\n

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Figure 5-2. FPGA Formal Technology Adoption<\/b><\/p>\n

One observation from these adoption trends is that the FPGA market has matured its verification processes, as I previously stated. This maturity is likely due to the growing complexity of designs as discussed in my previous blogs.<\/p>\n

In my next blog (click here<\/a>), I\u2019ll focus on FPGA design and verification language adoption trends, as identified by the 2018 Wilson Research Group study.<\/p>\n

Quick links to the 2018 Wilson Research Group Study results<\/h2>\n