{"id":12998,"date":"2018-01-30T12:18:05","date_gmt":"2018-01-30T19:18:05","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=12998"},"modified":"2026-03-27T08:42:23","modified_gmt":"2026-03-27T12:42:23","slug":"see-you-at-dvcon-u-s-2018","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2018\/01\/30\/see-you-at-dvcon-u-s-2018\/","title":{"rendered":"See You at DVCon U.S. 2018!"},"content":{"rendered":"

We hope to see you at DVCon U.S. 2018<\/strong><\/a>.\u00a0 Mentor will showcase 17 papers and posters during the conference on topics covering CDC, coverage, debug, formal, low power, safety-critical, Portable Stimulus, UVM and more.\u00a0 To attend, you can register here<\/strong><\/a>.\u00a0 DVCon broadens its topic reach this year to include automotive system design and verification.\u00a0 In keeping with this call, Mentor has a tutorial that targets automotive product safety and embrace ISO 26262.\u00a0 Below are a few highlights and some details about where you will find the Mentor team.<\/p>\n

\n

Automotive Safety<\/h3>\n

If you have attended DVCon U.S. the past few years, you know the design and verification challenges that highly complex SoC\u2019s have placed on traditional design have come into sharp focus.\u00a0 One of the driving factors for these challenges is the amount of electronics and embedded software the global transportation industry continues to add to their products.\u00a0 Systems and semiconductor makers must now consider the fault tolerance of their product offerings to this rapidly growing market.\u00a0 In the past, DVCon could focus on the RTL design and verification challenges\u00a0 alone.\u00a0 While good work was done to reduce the impact of errors in those systems, users had to tolerate personal computers that needed a reboot every now and then or a mobile device that could crash from time-to-time.\u00a0 But this cannot be tolerated in the emerging autonomous vehicles.\u00a0 Problems of the past that were an annoyance can be deadly when it comes to autonomous vehicles.\u00a0 Fortunately, the ISO 26262 standard defines the safety level of a design via specific safety goals, safety mechanisms, and fault metrics.\u00a0 Want to learn more?\u00a0 Need to learn more?\u00a0 Join us at the Mentor afternoon tutorial on Thursday to learn more and see how you can \u201cstay out of the news.\u201d<\/p>\n

Tutorial: Thursday March 1 | 2:00pm \u2013 5:30pm | Siskiyou Room
\nTitle: How to Stay Out of the News with ISO 26262 Compliant Verification<\/a><\/strong><\/p>\n

\n

Program Panel on Verification<\/h3>\n

Gone are the days when you could simply type in your RTL, simulate then go to silicon.\u00a0 Are you one who can remember that productivity was once measured by how fast you could type in your RTL code? Remember when that<\/em> was the bottleneck to a completed design?\u00a0 Again, DVCon attendees know those days are well behind us.\u00a0 How do we solve the hardest verification problems now?\u00a0 The Wednesday afternoon panel offers an opportunity to gain some insight from those who are applying emulation, simulation, formal verification and FPGA prototyping tools with a mix of methodologies, along with new and emerging standards to make the world\u2019s largest SoC\u2019s a reality.<\/p>\n

Panel: Wednesday February 28 | 1:30pm \u20132:30pm | Oak\/Fir Room
\nTitle: <\/strong>The Right Tool (or Tools) for the Toughest Verification Tasks<\/strong><\/a><\/p>\n

\n

Wednesday Lunchtime Keynote<\/h3>\n

Mentor’s lunchtime keynotes are always popular.\u00a0 This year will be no exception.\u00a0 We will focus on validation, verification\u2019s big brother.\u00a0 We know your insatiable need for speed feeds an ever increasing desire to achieve the highest productivity possible using simulation, emulation and prototyping.\u00a0 While we are feeding your body we will also feed your mind with ideas that will satisfy your craving for speed.<\/p>\n

Lunch: Wednesday February 28 | 12:00pm \u2013 1:15pm | Pine\/Cedar Room
\nTitle: <\/strong>Validation: Verification\u2019s Big Brother – “I Wanna Go Fast\u201d<\/strong><\/a><\/p>\n

\n

Exhibition and Product Demos<\/h3>\n

There will be three days of exhibition and product demos.\u00a0 This is always a great place to meetup.\u00a0 And at the end of each day, a social hour is a great way to start the evening.\u00a0 If you want to discuss more about what you learned in sessions, tutorials, over lunch or during panel sessions, we are ready to share and show you more.<\/p>\n

Exhibits: Mentor, A Siemens Business Booth #1101<\/a> <\/strong>(that\u2019s decimal 1101; if in binary, is it your “lucky” number? – if Hex, it’s not a good grade!)
\nMonday February 26 | 5:00pm \u2013 7:00pm
\nTuesday February 27 | 2:30pm \u2013 6:00pm
\nWednesday February 28 | 2:30pm \u2013 6:00pm<\/strong><\/p>\n

\n

Low-Power SoC\u2019s with Comprehensive Metrics-based Methodology<\/h3>\n

The past 10 years have seen consumer devices be the beneficiaries of reduced energy needs.\u00a0 With each reduction in the use of energy there is a nearly equal growth in design complexity to consume that reduction.\u00a0 To claim we are better now than 10 years ago and we don\u2019t have to worry about this for the next 10 years falls short of the continued demands that come from nomadic IoT devices, 5G networking, consumer devices, automotive products, wearables and more.\u00a0 The constant progress of technology that presses the need for system energy considerations will not abate nor will the impacts from regulatory and governmental bodies yield to conservation.\u00a0 Want to learn more?\u00a0 Join us at the Mentor morning tutorial in Thursday to learn from the experts.<\/p>\n

Tutorial: Thursday March 1 | 8:30am \u2013 12:00pm | Siskiyou Room
\nTitle: <\/strong>Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-Chips<\/strong><\/a><\/p>\n

\n

Accellera Day Tutorials<\/h3>\n

DVCon begins with Accellera Day which will feature a morning and afternoon tutorial with a lunch break hosted by Accellera Systems Initiative.\u00a0 Accellera will educate us with updates to its popular UVM standard and introduce us to more of the details of its emerging Portable Stimulus Standard.<\/p>\n

<\/a>Portable Test and Stimulus: The Next Level of Verification Productivity is Here<\/a><\/strong>
\nMonday February 26 | 9:00am \u2013 12:00pm | Oak\/Fir Room<\/strong><\/p>\n

This in-depth technical tutorial will focus on a set of typical design use-cases from a variety of applications and show how to use the emerging Portable Test and Stimulus Standard to create an abstract model of your verification intent. The tutorial will then demonstrate how these models can be used to generate scenarios to be executed on the different platforms and environments used in your development process, and how the models can be reused and leveraged from project to project.<\/p>\n

<\/a>IEEE-Compatible UVM Reference Implementation and Verification Components<\/a>
\nMonday February 26 | 2:00pm \u2013 5:00pm | Oak\/Fir Room<\/strong><\/p>\n

This tutorial will introduce engineers to the new reference implementation aligned with IEEE 1800.2 created by the Accellera UVM WG. The speakers will use the new reference implementation to describe the new features and changes relative to UVM 1.2. Engineers attending the tutorial will learn the steps they need to take to update their verification components to be IEEE-compatible. Code examples and interactive discussions with members of the Accellera UVM WG<\/a> will help engineers gain the practical knowledge they need to adopt the IEEE 1800.2\u2122 Standard for UVM.<\/p>\n","protected":false},"excerpt":{"rendered":"

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