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<\/p>\nThere\u2019s a wonderful quote in Brian Kernighan book The Elements of Programming Style, where he says \u201cEveryone knows that debugging is twice as hard as writing a program in the first place. So if you’re as clever as you can be when you write it, how will you ever debug it?\u201d Humor aside, our 2016 Wilson Research Group study supports the claim that debugging is a challenge today, where most projects spend more time involved in debugging than any other task. <\/p>\n
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One insidious aspect of debugging is that it is unpredictable if not properly managed. For example, from a management perspective, it is easy to gather metrics on various processes involved in the product development lifecycle from previous projects in order to plan for the future. However, the unpredictability of debugging becomes a manager\u2019s nightmare. Guidelines for efficient debugging are required to improve productivity.<\/p>\n
In reality, debugging is required in every process that spans a products development lifecycle, from conception, architectural design, implementation, post-silicon, and even the test and testbenches we create to verify\/validate a design. The emergence of SystemVerilog and UVM has necessitated the development of new debugging skills and tools. Traditional debugging approaches that were adopted for simple RTL testbenches have become less productive. To address this dearth of new debugging process knowledge I\u2019m excited to announce that the Verification Academy has just released a new UVM debugging course. This course consists of five video sessions. Topics that are covered in this course include:<\/p>\n
\u2022\tA historical perspective on the general debugging problem
\n\u2022\tWays to effectively debug memory leaks in UVM environments
\n\u2022\tHow to debug connectivity issues between UVM components
\n\u2022\tGuidelines to effectively debug common issues related to UVM phases
\n\u2022\tMethods to debug common issues with the UVM configuration database<\/p>\n