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<\/a><\/p>\nFortunately, the answer is relatively straightforward.\u00a0 In a nutshell, the top level UPF supply ports and supply nets provide hooks for the design, libraries, and annotated testbenches through the UPF connect_supply_net<\/strong> and connect_supply_set<\/strong> commands \u2013 these define the complete power network connectivity. Additionally, the top level UPF supply ports and supply nets are collectively known as supply pads or supply pins (e.g. VDD, VSS etc.), where the UPF low power standard recommends how supply pads may be referenced in the testbenches and extended to manipulate power network connectivity in a testbench simulation. Hence it becomes possible to control power \u2018On\u2019 and \u2018Off\u2019 for any power domain in the design through the supply pad referenced in the testbench.<\/p>\n All the necessary HDL testbench connections are done through importing UPF packages available under the power-aware simulation tool distribution environment. Even better: the IEEE 1801 LRM provides standard UPF packages for Verilog, SystemVerilog, and VHDL testbenches to import the appropriate UPF packages to manipulate the supply pads of the design under verification. The following are syntax examples for UPF packages to be imported or used in different HDL variants. Note: UPF packages can be imported within or outside of the module-endmodule<\/strong> declaration.<\/p>\n Example UPF package setup for a VHDL testbench<\/u><\/p>\n The \u201cimport UPF::*<\/strong>\u201d package and \u201cuse ieee.UPF.all;<\/strong>\u201d library actually embeds the functions that are used to utilize and drive the design supply pads directly from the testbench. Thus, once these packages are referenced in the testbench, the simulator automatically searches for them from the simulator installation locations and makes the built-in functions of these packages available to utilize in the simulation environment. The following examples explain these functions, namely supply_on<\/strong> and supply_off<\/strong> with their detailed arguments.<\/p>\n Example functions for Verilog and SystemVerilog testbenches to drive supply pads<\/u><\/p>\n Note: Questa Power Aware Simulator (PA SIM) users do not have to deal with the third argument, string file_info = “”<\/strong> \u2013 Questa will automatically take care of this.<\/p>\n Example functions for a VHDL testbench driving supply pads<\/u><\/p>\n Regardless of the language used, the pad_name<\/strong> must be a string constant, and a valid top level UPF supply port must be passed to this argument along with a \u201cnon-zero\u201d real value to denote power \u201cOn\u201d, or \u201cempty\u201d to denote power \u201cOff\u201d. Questa PA-SIM will obtain the top module design name from the UPF set_scope<\/strong> commands defined below.<\/p>\n Now that the basic package binding and initial wiring is setup, how do you actually control the design supply pad through a testbench?\u00a0 This is where the aforementioned UPF connect_supply_net<\/strong> or connect_supply_set<\/strong> and set_scope<\/strong> commands come in, as per the following code examples.<\/p>\n Example UPF<\/strong> with <\/u>connect_supply_net<\/u><\/strong> for utilizing supply pads from the testbench<\/u><\/p>\n Next, the UPF connect_supply_net<\/strong> specified supply ports VDD_A, VDD_B, VSS, etc. can be directly driven from the testbench as shown in the following code example.<\/p>\n That\u2019s all there is to it!<\/p>\n As you can glean from the examples, it is pretty easy to design a voltage regulator or a power management unit in the testbench through the functions supply_on<\/strong> and supply_off<\/strong> to mimic a real chip\u2019s power operations. Of course there are many more functions available under these UPF packages, but hopefully this article is enough to get you started.<\/p>\n Joe Hupcey III Related posts:<\/strong><\/p>\n Part 11: The 2016 Wilson Research Group Functional Verification Study on ASIC\/IC Low Power Trends<\/p>\n 3 Things About UPF 3.0 You Need to Know Now<\/p>\n Whitepaper: Advanced Verification of Low Power Designs<\/p>\n","protected":false},"excerpt":{"rendered":" Face facts: power supply nets are now effectively functional nets, but they are typically not defined in the design\u2019s RTL….<\/p>\n","protected":false},"author":71594,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[577,664,751,758,785,831,833],"industry":[],"product":[],"coauthors":[],"class_list":["post-12711","post","type-post","status-publish","format-standard","hentry","category-news","tag-low-power","tag-questa-pa-sim","tag-systemverilog","tag-testbench","tag-upf","tag-verilog","tag-vhdl"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/12711","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71594"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=12711"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/12711\/revisions"}],"predecessor-version":[{"id":17591,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/12711\/revisions\/17591"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=12711"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=12711"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=12711"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=12711"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=12711"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=12711"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
\nExample of UPF package setup for Verilog or SystemVerilog testbench<\/u><\/p>\nimport UPF::*;
\nmodule testbench;
\n...
\nendmodule<\/strong><\/code><\/p>\nlibrary ieee;
\nuse ieee.UPF.all;<\/strong><\/code><\/p>\nentity dut is
\n...
\nend entity;<\/strong><\/code><\/p>\narchitecture arch of dut is<\/strong><\/code><\/p>\nbegin
\n...
\nend arch;<\/strong><\/code><\/p>\nsupply_on( string pad_name, real value = 1.0, string file_info = \"\");<\/strong><\/code><\/p>\nsupply_off( string pad_name, string file_info = \"\" );<\/strong><\/code><\/p>\nsupply_on ( pad_name : IN string ; value : IN real ) return boolean;<\/strong><\/code><\/p>\nsupply_off ( pad_name : IN string ) return boolean;<\/strong><\/code><\/p>\nset_scope cpu_top
\ncreate_power_domain PD_top
\n......<\/strong><\/code><\/p>\n# IMPLEMENTATION UPF Snippet
\n# Create top level power domain supply ports
\ncreate_supply_port VDD_A -domain<\/em> PD_top
\ncreate_supply_port VDD_B -domain PD_top
\ncreate_supply_port VSS -domain PD_top<\/strong><\/code><\/p>\n# Create supply nets
\ncreate_supply_net VDD_A -domain<\/em> PD_top
\ncreate_supply_net VDD_B -domain<\/em> PD_top
\ncreate_supply_net VSS -domain<\/em> PD_top<\/strong><\/code><\/p>\n# Connect top level power domain supply ports to supply nets
\nconnect_supply_net<\/em> VDD_A -ports<\/em> VDD_A
\nconnect_supply_net<\/em> VDD_B -ports<\/em> VDD_B
\nconnect_supply_net<\/em> VSS -ports<\/em> VSS<\/strong><\/code><\/p>\nimport UPF::*;
\nmodule testbench;
\n...
\nreg VDD_A, VDD_B, VSS;
\nreg ISO_ctrl;
\n...
\ninitial begin
\n#100
\nISO_ctrl = 1\u2019b1;
\nsupply_on (VDD_A, 1.10); \/\/ Values represent voltage & non zero value<\/strong><\/code><\/p>\n\/\/ (1.10) signifies Power On<\/strong><\/code><\/p>\nsupply_on (VSS, 0.0); \/\/ UPF LRM Specifies Ground VSS On at 0.0
\n...
\n#200
\nsupply_on (VDD_B, 1.10);
\n...
\n#400
\nsupply_off (VDD_A); \u00a0 \/\/ empty real value argument indicates Power Off<\/strong><\/code><\/p>\n...
\nend
\nendmodule<\/strong><\/code><\/p>\n
\nProgyna Khondkar
\nfor the Questa Low Power Design & Verification product team<\/p>\n