{"id":12636,"date":"2016-12-06T14:46:30","date_gmt":"2016-12-06T21:46:30","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=12636"},"modified":"2026-03-27T08:38:02","modified_gmt":"2026-03-27T12:38:02","slug":"emulation-and-simulation-invaluable-tools-for-ic-verification","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2016\/12\/06\/emulation-and-simulation-invaluable-tools-for-ic-verification\/","title":{"rendered":"Emulation and simulation; invaluable tools for IC verification"},"content":{"rendered":"

Emulation technology has been around for a long time\u2014more than four decades by my count\u2014and industry observers believe more than ever that it\u2019s a key ingredient in the IC verification strategy, albeit with a rebirth. The question is, what is this new era of emulation all about and why is hardware emulation, which remained on the fringes of IC design ecosystem with a small customer base for many years, now becoming a mainstream design tool for system-on-chip (SoC) verification? The answer can be found in the advent of bigger and more complex chips that often contain multiple processor cores and exceed 100 million gates.<\/p>\n

In a nutshell, a register-transfer-level (RTL) simulator, a go-to verification tool is being challenged as design capacity surpasses 100 million gates.\u00a0 Greater gate counts are possible because of the scaling roadmap for processors.\u00a0 After all, there is only so much you can do with multi-threading. Next, even hardware-description-language<\/em> (HDL) software simulators running in parallel over PC farms don\u2019t create a viable option because design-under-test (DUT) environments are sequential in nature.<\/p>\n

On the other hand, hardware emulation, once the staple of large IC designs like processors and graphic chips, is now becoming a popular verification tool precisely because it runs faster than HDL simulators for full-chip verification. A hardware emulation tool can run the verification of large, SoC designs over 10 times and sometimes much greater than 10 times faster than software simulation.<\/p>\n

\"Graphic<\/a><\/em><\/p>\n

The view of the key verification modes supported by <\/em>Mentor Graphics\u2019 Veloce emulator platform<\/em><\/a>.<\/em><\/p>\n

Hardware emulation has been steadily evolving over the past decade or so, as the cost of ownership is coming down while emulation tools are becoming easier to install and operate. And with the changing equation of emulator ROI and SoC design imperatives, an increasing number of IC designers are inclined to use emulation tools for debugging the hardware and testing hardware and software integration. Moreover, emulation tools are becoming more versatile, ranging from in-circuit emulation (ICE), where physical devices are cabled to the emulator, to more innovative co-emulation solutions like Veloce VirtuaLAB<\/a> that virtualizes the interfaces amid the growing functionality of today\u2019s SoC designs.<\/p>\n

Software simulation or hardware emulation<\/strong><\/p>\n

A simulator tries to model the behavior of the SoC or system-level design while an emulator creates an actual implementation of the design. Here, it\u2019s important to note that both software simulators and hardware emulators are employed for design verification\u2014a stage also known as design-under-test or DUT\u2014where a compiler converts the design model into a data structure stored in memory.<\/p>\n

However, in the case of simulation, a software algorithm processes the data representing a design model using a design language, while an emulator processes the data structure using a compute engine enabled by a processor array. Although hardware emulation is growing beyond a $300 million market, it doesn\u2019t mean that it\u2019s going to be the end of the road for HDL simulation tools.<\/p>\n

 <\/p>\n

\u00a0\"large<\/a><\/em><\/p>\n

The <\/em>Veloce emulator<\/a>, which supports both traditional ICE and transaction-based verification, runs verification of SoCs with multiple protocol interfaces.<\/em><\/p>\n

HDL-based software simulation will most likely remain the verification engine of choice, especially at the early stage of verification process\u2014for instance, at the IP and subsystem levels\u2014as it represents an economical, easy-to-use, and quick-to-setup EDA tool<\/a>. On the other hand, emulation will gain traction in larger SoC designs that encompass millions of verification cycles and where hardware bugs are difficult to find. In other words, the two EDA<\/a> tool markets for SoC and system-level design verification will co-exist for the foreseeable future.<\/p>\n","protected":false},"excerpt":{"rendered":"

Emulation technology has been around for a long time\u2014more than four decades by my count\u2014and industry observers believe more than…<\/p>\n","protected":false},"author":71595,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[429,457,459,517,524,718,721,816,819,840],"industry":[],"product":[],"coauthors":[],"class_list":["post-12636","post","type-post","status-publish","format-standard","hentry","category-news","tag-design","tag-emulation","tag-emulator","tag-hardware","tag-ice","tag-simulation","tag-soc","tag-veloce","tag-verification","tag-virtualab"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/12636","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71595"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=12636"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/12636\/revisions"}],"predecessor-version":[{"id":19838,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/12636\/revisions\/19838"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=12636"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=12636"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=12636"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=12636"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=12636"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=12636"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}