{"id":12430,"date":"2016-09-21T11:30:34","date_gmt":"2016-09-21T18:30:34","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=12430"},"modified":"2026-03-27T08:37:45","modified_gmt":"2026-03-27T12:37:45","slug":"part-6-the-2016-wilson-research-group-functional-verification-study","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2016\/09\/21\/part-6-the-2016-wilson-research-group-functional-verification-study\/","title":{"rendered":"Part 6: The 2016 Wilson Research Group Functional Verification Study"},"content":{"rendered":"

FPGA Language and Library Trends<\/strong><\/p>\n

This blog is a continuation of a series of blogs related to the 2016 Wilson Research Group Functional Verification Study (click here<\/a>). \u00a0In my previous blog (click here<\/a>), I focused on FPGA verification techniques and technologies adoption trends, as identified by the 2016 Wilson Research Group study. In this blog, I\u2019ll present FPGA design and verification language trends.<\/p>\n

You might note that the percentage for some of the language that I present sums to more than one hundred percent. The reason for this is that many FPGA projects today use multiple languages.<\/p>\n

FPGA RTL Design Language Adoption Trends<\/strong><\/p>\n

Let\u2019s begin by examining the languages used for FPGA RTL design. Figure 1 shows the trends in terms of languages used for design, by comparing the 2012, 2014, and 2016 Wilson Research Group study, as well as the projected design language adoption trends within the next twelve months. Note that the language adoption is declining for most of the languages used for FPGA design with the exception of Verilog and SystemVerilog.<\/p>\n

Also, it\u2019s important to note that this study focused on languages used for RTL design. We have conducted a few informal studies related to languages used for architectural modeling\u2014and it\u2019s not too big of a surprise that we see increased adoption of C\/C++ and SystemC in that space. However, since those studies have (thus far) been informal and not as rigorously executed as the Wilson Research Group study, I have decided to withhold that data until a more formal study can be executed related to architectural modeling and virtual prototyping.<\/p>\n

\"BLOG-2016-WRG-figure-6-1\"<\/p>\n

Figure 1. Trends in languages used for FPGA design<\/strong><\/p>\n

It\u2019s not too big of a surprise that VHDL is the predominant language used for FPGA RTL design, although it is slowly declining when viewed as a worldwide trend. An important note here is that if you were to filter the results down by a particular market segment or region of the world, you would find different results. For example, if you only look at Europe, you would find that VHDL adoption as an FPGA\u00a0design language is about 79 percent, while the world average is 62 percent. However, I believe that it is important to examine worldwide trends to get a sense of where the industry is moving in the future.<\/p>\n

FPGA Verification Language Adoption Trends<\/strong><\/p>\n

Next, let\u2019s look at the languages used to verify FPGA designs (that is, languages used to create simulation testbenches). Figure 2 shows the trends in terms of languages used to create simulation testbenches by comparing the 2012, 2014, and 2016 Wilson Research Group study, as well as the projected verification language adoption trends within the next twelve months.<\/p>\n

\"BLOG-2016-WRG-figure-6-2\"<\/p>\n

Figure 2. Trends in languages used in verification to create FPGA simulation testbenches<\/strong><\/p>\n

What is interesting in 2016 is that SystemVerilog overtook VHDL as the language of choice for building FPGA testbenches. But please note that the same comment related to design language adoption applies to verification language adoption. That is, if you were to filter the results down by a particular market segment or region of the world, you would find different results. For example, if you only look at Europe, you would find that VHDL adoption as an FPGA\u00a0verification language is about 66 percent (greater than the worldwide average), while SystemVerilog adoption is 41 percent (less than the worldwide average).<\/p>\n

FPGA Testbench Methodology Class Library Adoption Trends<\/strong><\/p>\n

Now let\u2019s look at testbench methodology and class library adoption for FPGA designs. Figure 3 shows the trends in terms of methodology and class library adoption by comparing the 2012, 2014, and 2016 Wilson Research Group study, as well as the projected verification language adoption trends within the next twelve months.<\/p>\n

\"BLOG-2016-WRG-figure-6-3\"<\/p>\n

Figure 3. FPGA methodology and class library adoption trends<\/strong><\/p>\n

Today, we see a basically a flat or downward trend in terms of adoption of all testbench methodologies and class libraries with the exception of UVM, which has been growing at a healthy 10.7 percent compounded annual growth rate. The study participants were also asked what they plan to use within the next 12 months, and based on the responses, UVM is projected to increase an additional 12.5 percent.<\/p>\n

By the way, to be fair, we did get a few write-in methodologies, such as OSVVM and UVVM that are based on VHDL. I did not list them in the previous figure since it would be difficult to predict an accurate adoption percentage. The reason for this is that they were not listed as a selection option on the original question, which resulted in a few write-in answers. Nonetheless, the data suggest that the industry momentum and focused has moved to SystemVerilog and UVM.<\/p>\n

FPGA Assertion Language and Library Adoption Trends<\/strong><\/p>\n

Finally, let\u2019s examine assertion language and library adoption for FPGA designs. The 2016 Wilson Research Group study found that 47 percent of all the FPGA projects have adopted assertion-based verification (ABV) as part of their verification strategy. The data presented in this section shows the assertion language and library adoption trends related to those participants who have adopted ABV.<\/p>\n

Figure 4 shows the trends in terms of assertion language and library adoption by comparing the 2012, 2014, and 2016 Wilson Research Group study, and the projected adoption trends within the next 12 months. The adoption of SVA continues to increase, while other assertion languages and libraries are not trending at significant changes.<\/p>\n

\"BLOG-2016-WRG-figure-6-4\"<\/strong><\/p>\n

Figure 4. Trends in assertion language and library adoption for FPGA designs<\/strong><\/p>\n

In my next blog (click here<\/a>), I will shift the focus of this series of blogs and start to present the ASIC\/IC findings from the 2016 Wilson Research Group Functional Verification Study.<\/p>\n

Quick links to the 2016 Wilson Research Group Study results<\/strong><\/p>\n