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Join us at the 53rd Design Automation Conference<\/h3>\nJoin us at the 53rd Design Automation Conference<\/h3>\nDAC is always a time of jam-packed activity with multiple events that merit your time and attention.\u00a0 As you prepare your own personal calendars and try your best to reduce or eliminate conflicts, let me share with you some candidate events that you may wish to consider having on your calendar.\u00a0 I will highlight opportunities to learn more about ongoing and emerging standards from Accellera and IEEE.\u00a0 I will focus on a few sessions at the Verification Academy booth (#627) that feature Partner presentations.\u00a0 And I will spotlight some venues where other industry collaboration will be detailed.\u00a0 You will also find me at many of these events as well.<\/p>\n
Accellera will host its traditional Tuesday morning breakfast.\u00a0 Registration is required \u2013 or you might not find a seat.\u00a0 As always, breakfast is free.\u00a0 The morning will feature a \u201cTown Hall\u201d style meeting that will cover UVM (also known as IEEE P1800.2) and other technical challenges that could help evolve UVM into other areas.\u00a0\u00a0 Find out more and learn about all things UVM, register here<\/strong><\/a>.<\/p>\n The Verification Academy is \u201cpartner-central\u201d for us this year.\u00a0 Each day will feature partner presentations that highlight evolving design and verification methodologies, standards support and evolution, and product integrations.\u00a0 Verification Academy is booth #627<\/strong><\/a>, which is centrally located and easy to find.\u00a0 Partner presentations include:<\/p>\n Modern development approaches are leaving quality gaps that advanced verification techniques fail to address… and the gaps are growing in spite of new innovation. It’s time for a fun, frank and highly interactive discussion around the shortcomings of today’s advanced verification methods.<\/li>\n SystemVerilog Assertions (SVA) can be added directly to the RTL code or be added indirectly through bindfiles. 13 years of professional SVA usage strongly suggests that Best Known Practices use bindfiles to add assertions to RTL code.<\/li>\n Using an Ethernet Controller design, we show how complete verification can be done in an automated manner, saving time while improving quality. Integration of two tools will be shown. InFact creates tests for a variety of scenarios which is more efficient and exhaustive than a pure constrained random methodology. ISequenceSpec forms a layer of abstraction around the IP\/SoC from a specification.<\/li>\n The traditional environments for safety-related hardware and software such as avionics, rail and nuclear have been joined by others (such as automotive and medical devices) as systems become increasingly complex and ever more reliant on embedded software. In tandem, further industry-specific safety standards (including ISO 26262 for automotive applications and IEC 62304 for medical device software) have been introduced to ensure that hardware and software in these application areas has been developed and tested to achieve a defined level of integrity. In this presentation, we will be explaining some of these changes and how they can be implemented.<\/li>\n In December 2015, Oski challenged formal users to solve a chessboard problem. This was an opportunity to show how nifty formal techniques might be used to solve a fun puzzle. Design verification engineers from a variety of semiconductor companies and research labs participated in the contest. The techniques submitted by participants presented a number of worthy solutions, with varying degrees of success.<\/li>\n<\/ul>\n Debug Data API:<\/strong> \u201cCadence and Mentor Demonstrate Collaboration for open Debug Data API in Action\u201d\u00a0 It was just a year ago that the project to create an open debug data API was announced at DAC 52.\u00a0 Since there several possible implementation styles were reviewed, an agreed specification created and early working prototypes demonstrated.\u00a0 On Tuesday, June 7th at 2:00pm we will host a session at the Verification Academy (Booth #627<\/strong><\/a>).\u00a0 You are encouraged to register<\/strong><\/a> for the free session \u2013 but walkups are always welcome!\u00a0 You can find more information here<\/strong><\/a>.<\/p>\n Portable Stimulus Tutorial:<\/strong> \u201cHow Portable Stimulus Addresses Key Verification, Test Reuse, and Portability Challenges\u201d\u00a0 As part of the official DAC program, there will be a tutorial on the emerging standardization work in Accellera.\u00a0 The tutorial is Monday, June 6th from 1:30pm \u2013 3:00pm in the Austin Convention Center, Room 15.\u00a0 You can register<\/strong><\/a> here for the tutorial.\u00a0 There is a fee for this event.\u00a0 Want to know more about the tutorial?\u00a0 You can find more information here<\/strong><\/a>.<\/p>\n It is always good to end the day on a light note.\u00a0 To that end, on Monday June 6th, will invite you to \u201cgrab a cold one\u201d at the Verification Academy booth and continue discussions and networking with your colleagues.\u00a0 If past year\u2019s experience is any guide to this year, you may want to get here early for your drink!\u00a0 There is no registration to guarantee a drink, unfortunately!\u00a0 So, come early; stay late!\u00a0 See you in Austin!<\/p>\n And if you miss me at any of the locations above, tweet me @dennisbrophy \u2013 your message is sure to reach me right away.<\/p>\n","protected":false},"excerpt":{"rendered":" Join us at the 53rd Design Automation Conference DAC is always a time of jam-packed activity with multiple events that…<\/p>\n","protected":false},"author":71541,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[314,326,337,389,409,420,528,621,632,638,732,744,745,751,772,787,820,854],"industry":[],"product":[],"coauthors":[],"class_list":["post-12222","post","type-post","status-publish","format-standard","hentry","category-news","tag-1800-2","tag-accellera","tag-agnisys","tag-collaboration","tag-dac","tag-debug-data-api","tag-ieee","tag-oski-technology","tag-partners","tag-portable-stimulus","tag-standards","tag-sunburst-design","tag-sva","tag-systemverilog","tag-tvs","tag-uvm","tag-verification-academy","tag-xtremeeda"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/12222","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71541"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=12222"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/12222\/revisions"}],"predecessor-version":[{"id":14585,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/12222\/revisions\/14585"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=12222"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=12222"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=12222"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=12222"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=12222"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=12222"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}Partners<\/h3>\n
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Back to the Stone Ages for Advanced Verification
\nMonday June 6th
\n2:00 PM | Neil Johnson \u2013 XtremeEDA<\/h4>\nSystemVerilog Assertions – Bind files & Best Known Practices
\nMonday June 6th
\n3:00 PM | Cliff Cummings – Sunburst Design<\/h4>\nSpecification to Realization flow using ISequenceSpec\u2122 and Questa\u00ae InFact
\nTuesday June 7th
\n10:00 AM | Anupam Bakshi – Agnisys, Inc.<\/h4>\nSafety Critical Verification
\nWednesday June 8th
\n10:00 AM | Mike Bartley – TVS<\/h4>\nUsing a Chessboard Challenge to Discover Real-world Formal Techniques
\nWednesday June 8th
\n3:00 PM | Vigyan Singhal & Prashant Aggarwal – Oski Technology<\/h4>\nIndustry Collaboration<\/h3>\n
Fun<\/h3>\n