{"id":12120,"date":"2016-02-24T11:22:18","date_gmt":"2016-02-24T18:22:18","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=12120"},"modified":"2026-03-27T08:37:08","modified_gmt":"2026-03-27T12:37:08","slug":"portable-stimulus-applications-at-dvcon-2016","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2016\/02\/24\/portable-stimulus-applications-at-dvcon-2016\/","title":{"rendered":"Portable Stimulus Applications at DVCon 2016"},"content":{"rendered":"

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It\u2019s that time of the year again \u2013 time for verification engineers and vendors alike to show off the state of the art in design verification at DVCon 2016. Last year at DVCon, Accellera\u2019s Portable Stimulus Proposed Working Group (PSPWG) was transformed into a full-fledged Working Group (PSWG) with the charter to accept contributions and define a stimulus specification standard that enables the definition of stimulus that is portable from block to system level verification, and portable across the verification engines \u2013 simulation, emulation, and FPGA prototype.<\/p>\n

\"pss\"<\/a><\/p>\n

It\u2019s been a busy year in the Portable Stimulus Working Group. We\u2019ve spent time discussing, understanding, and clarifying usage examples contributed by user companies, whose purpose it is to help illustrate how a portable stimulus specification addresses industry verification challenges. We\u2019ve spent time reviewing and understanding language contributions from vendors and users. With all of this activity and focus around a specification that still (at least in its entirety) lives on paper, I\u2019m sure it would easy for an observer to lose sight of the fact that there are Portable Stimulus tools already in the market that are providing great results to production users. DVCon is a great reminder that, while the Portable Stimulus Specification standard is in process, Portable Stimulus is here now!<\/p>\n

To learn more about how users are applying Portable Stimulus, attend the SystemVerilog Programming and Techniques <\/em>session on Tuesday afternoon. Microsoft will be presenting a paper about techniques using the Questa inFact Graph-Based Portable Stimulus tool for efficient bug hunting.<\/p>\n

If you\u2019re curious about how existing descriptions, specifically SystemVerilog, relate to the emerging standard, drop by my poster on Tuesday morning. My paper and poster present guidelines for structuring SystemVerilog to make portions easily reusable in a Portable Stimulus Specification description.<\/p>\n

Of course, Portable Stimulus appears in other places at DVCon too! Check out the full program to find other papers and tutorials highlighting how Portable Stimulus is providing value to users today!<\/p>\n

If you\u2019d like to learn more about Portable Stimulus, or just discuss verification techniques in general, drop by the Verification Academy booth on the exhibition floor. I\u2019ll be there, as will Mentor\u2019s standards and methodology experts Harry Foster, Tom Fitzpatrick, Dennis Brophy, and others. So, come find us. I\u2019d love to hear your thoughts on Portable Stimulus, and getting to interact with other verification practitioners is truly the best part of DVCon!<\/p>\n","protected":false},"excerpt":{"rendered":"

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