![\"Uvm](\"https:\/\/blogs.mentor.com\/verificationhorizons\/files\/2015\/10\/uvm_logo.png\" "\\"uvm_logo.png\\""){kind=logo}
<\/a>For everyone involved in the functional verification of electronic systems, you know about the Universal Verification Methodology (UVM) and are probably using it in one fashion or another. \u00a0And if you have been reading this blog, you have undoubtedly seen blogs by Harry Foster<\/a> on the adoption and use of UVM by the FPGA<\/a> and ASIC\/SoC<\/a> community. \u00a0It has clearly become the world\u2019s most popular and accepted verification methodology. \u00a0It is odd to point out that with this popularity, there has not been a UVM-only event to bring UVM users together this year. \u00a0We believe it is time for UVM users to come together to explore its use and share productivity tips and tricks with each other. \u00a0You are invited to register and attend. \u00a0The details of the event are:<\/p>\n\u00a0 \u00a0 \u00a0 \u00a0\u00a0\u00a0 Event:<\/strong> UVM Forum – Verification Academy Live Seminar If you are an UVM Expert<\/em>, and already know just about everything about UVM, you might be interested in some new <\/em>topics that will be introduced and expanded upon. \u00a0Here are four:<\/p>\n The first is UVM Framework<\/em>. \u00a0UVM Framework supports reuse across projects, sites and companies from block to chip to system for both simulation and emulation.\u00a0 Those using it have seen at least a four week reduction in verification product schedules.<\/p>\n The second is Verification IP<\/em><\/strong>. \u00a0VIP can help you overcome your IP verification challenges. \u00a0One session will explore integrating VIP into a UVM environment with examples based on protocols such as AMBA\u00ae, MIPI\u00ae and PCI Express\u00ae. \u00a0If you are not an expert on a specific protocol, you can use VIP to drive stimulus and verify protocol compliance for you.<\/p>\n The third is Automating Scenario-Level UVM Test with Portable Stimulus<\/em><\/strong>. \u00a0In this session you will learn to rise above the transaction level to make scenario creation more productive. \u00a0You will learn how to leverage lower-level descriptions, such as sequence items, into larger scenarios. \u00a0You will learn how to leverage graph-based methods to efficiently and predicable exercise the scenario space to deliver high quality verification results. \u00a0It should also be noted, that an ongoing Accellera Working Group is exploring standardization of Portable Stimulus. \u00a0While Accellera working group details are not part of the session, UVM Forum attendees might consider augmenting their knowledge by visiting the Accellera Portable Stimulus<\/a> group.<\/p>\n The fourth is\u00a0Improved UVM Testbench Debug Productivity and Visibility<\/strong>. \u00a0For those who debug UVM on a daily basis, you might hear a common question \u201cAre we having fun yet?\u201d asked.\u00a0 The debug of UVM can be particularly difficult. \u00a0We will have a session to show you how to navigate complex UVM environments to quickly find your way around the code – whether its your own or inherited. \u00a0You will see how SystemVerilog\/UVM dynamic class activity is as easy to debug as it is with RTL signals. \u00a0Want to learn how to solve the top 10 common UVM bring-up issues with config_db<\/em>, the factory<\/em>, and sequence <\/em>execution? \u00a0Attend and you will learn.<\/p>\n While I can\u2019t promise that if you come as a novice you will leave as an expert, you can learn about UVM in the morning as one of the sessions is a technology overview to ensure you won\u2019t be lost when the experts speak. \u00a0If you know very little about UVM, the UVM Forum will help you. \u00a0There will be a couple presentations from UVM users. \u00a0One session is on how UVM enabled advanced storage IP silicon success (presented by Micron) and another session on UVM and emulation to ease the path to advanced verification and analysis (presented by Qualcomm).<\/p>\n I look forward to seeing you there.<\/p>\n","protected":false},"excerpt":{"rendered":" Verification Academy Brings “UVM Live” to the Santa Clara Convention Center For everyone involved in the functional verification of electronic…<\/p>\n","protected":false},"author":71541,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[457,638,702,718,751,787,789,794,799,825,835],"industry":[],"product":[],"coauthors":[],"class_list":["post-11991","post","type-post","status-publish","format-standard","hentry","category-news","tag-emulation","tag-portable-stimulus","tag-scenarios","tag-simulation","tag-systemverilog","tag-uvm","tag-uvm-accelleration","tag-uvm-debug","tag-uvm-framework","tag-verification-ip","tag-vip"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/11991","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71541"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=11991"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/11991\/revisions"}],"predecessor-version":[{"id":14588,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/11991\/revisions\/14588"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=11991"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=11991"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=11991"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=11991"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=11991"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=11991"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
\n\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 Location: <\/strong>Santa Clara Convention Center, Santa Clara, CA USA
\n\u00a0 \u00a0 \u00a0\u00a0 \u00a0\u00a0 Date: <\/strong>17 November 2015
\n\u00a0 \u00a0 \u00a0\u00a0 \u00a0\u00a0 Time:<\/strong> 8:30 a.m. – 4:00 p.m. PT
\n \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 More Information & Agenda:<\/strong> Click Here
\n<\/a>\u00a0 \u00a0 \u00a0\u00a0 \u00a0\u00a0 Register: <\/strong>Click Here<\/a><\/p>\nExperts Learn Something\u00a0New<\/h2>\n
Novices Welcome (and will learn something too!)<\/h2>\n
![\"\"](\"https:\/\/verificationacademy.com\/sites\/default\/files\/styles\/large\/public\/course_basic_uvm_tfitzpatrick_0.jpg?itok=OdWCiXf5\")
<\/a>Still want to know more before you attend?\u00a0 You can also boost your UVM\u00a0knowledge by attending an online UVM Basics course at Verification Academy. \u00a0Visit here<\/a> to learn more about the UVM Basics course.\u00a0 The Basic UVM course consists of 8 sessions with over an hour of instructional content. This course is primarily aimed at existing VHDL and Verilog engineers or managers who recognize they have a functional verification problem but have little or no experience with constrained random verification or object-oriented programming. The goal of the course is to raise the level of UVM knowledge to the point where users have sufficient confidence in their own technical understanding that it becomes less of a barrier to adoption – and makes the UVM Forum 2015 more meaningful for you.<\/p>\n