{"id":11901,"date":"2015-08-25T21:20:05","date_gmt":"2015-08-26T04:20:05","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=11901"},"modified":"2026-03-27T08:36:46","modified_gmt":"2026-03-27T12:36:46","slug":"ready-for-a-verification-extravaganza-in-the-land-of-verification-engineers","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2015\/08\/25\/ready-for-a-verification-extravaganza-in-the-land-of-verification-engineers\/","title":{"rendered":"Ready for a Verification Extravaganza in the Land of Verification Engineers?"},"content":{"rendered":"<p>I have always been wanting to contribute to the growing verification engineering community in India, which Mentor\u2019s CEO Wally Rhines calls \u201cthe largest verification market in the world\u201d. So when I first accompanied the affable Dennis Brophy to the IEEE India office back in April of 2014 to discuss the possibility of having a DVCon in India, I knew I was at the right place at the right time and it was opportunity to contribute to this community.<\/p>\n<p>I has been two years since that meeting, I don\u2019t have to write about how big a success the first ever DVCon India in 2014 was. I\u2019m glad I played a small part by being on the Technical Program Committee on the DV track, reviewing various abstracts. It is a responsibility which I thoroughly enjoyed. This year in addition to being on the TPC, I am contributing as the Chair for Tutorials and Posters. I am eagerly looking forward to the second edition of the Verification Extravaganza which is on 10<sup>th<\/sup> and 11<sup>th<\/sup> Sept 2015 and the amazing agenda we have planned for attendees.<\/p>\n<p>Day 1 of the conference is dedicated to keynotes, panel discussions and tutorials while day 2 is dedicated fully to Papers with a DV track and a panel in addition to papers in a ESL track. Participants are free to attend any track and can move between tracks. This year we had many sponsored tutorials submissions hence, there will be three parallel tutorial tracks, one on the DV side and two on the ESL track.<\/p>\n<p>Below please find a list of those that Mentor Graphics will be presenting at:<\/p>\n<ul>\n<li><strong>Keynote from Harry Foster discussing the growing complexity across the entire design ecosystem <\/strong><br \/>\nThursday, September 10, 2015<br \/>\n9:45am \u2013 10:30am<br \/>\nGrand Ball Room, The Leela Palace<br \/>\n<a href=\"http:\/\/dvcon-india.org\/conf\/program-at-a-glance\/\" target=\"_blank\" rel=\"noopener noreferrer\"><strong>More Information &gt;<\/strong><br \/>\n<\/a><a href=\"http:\/\/dvcon-india.org\/registration\/\" target=\"_blank\" rel=\"noopener noreferrer\"><strong>Register for this event &gt;<\/strong><\/a><\/li>\n<\/ul>\n<ul>\n<li><strong>Creating SystemVerilog UVM Testbenches for Simulation and Emulation Platform Portability to Boost Block-to-System Verification Productivity<\/strong><br \/>\nThursday, September 10, 2015<br \/>\n1:30pm \u2013 3:00pm<br \/>\nDV Track, Diya, The Leela Palace<br \/>\n<a href=\"http:\/\/dvcon-india.org\/conf\/program-at-a-glance\/\" target=\"_blank\" rel=\"noopener noreferrer\"><strong>More Information &gt;<\/strong><br \/>\n<\/a><a href=\"http:\/\/dvcon-india.org\/registration\/\" target=\"_blank\" rel=\"noopener noreferrer\"><strong>Register for this event &gt;<\/strong><\/a><\/li>\n<\/ul>\n<ul>\n<li><strong>Leveraging Portable Stimulus across Domains and Disciplines<\/strong><br \/>\nThursday, September 10, 2015<br \/>\n1:30pm \u2013 3:00pm<br \/>\nESL Track, Royal Ball Room, The Leela Palace<br \/>\n<a href=\"http:\/\/dvcon-india.org\/conf\/program-at-a-glance\/\" target=\"_blank\" rel=\"noopener noreferrer\"><strong>More Information &gt;<\/strong><br \/>\n<\/a><a href=\"http:\/\/dvcon-india.org\/registration\/\" target=\"_blank\" rel=\"noopener noreferrer\"><strong>Register for this event &gt;<\/strong><\/a><\/li>\n<\/ul>\n<ul>\n<li><strong>Expediting the code coverage closure using Static Formal Techniques &#8211; A proven approach at block and SoC Levels!<\/strong><br \/>\nThursday, September 10, 2015<br \/>\n1:30pm \u2013 3:00pm<br \/>\nDV Track, Grand Ball Room, The Leela Palace<br \/>\n<a href=\"http:\/\/dvcon-india.org\/conf\/program-at-a-glance\/\" target=\"_blank\" rel=\"noopener noreferrer\"><strong>More Information &gt;<\/strong><br \/>\n<\/a><a href=\"http:\/\/dvcon-india.org\/registration\/\" target=\"_blank\" rel=\"noopener noreferrer\"><strong>Register for this event &gt;<\/strong><\/a><\/li>\n<\/ul>\n<ul>\n<li><strong>FPGA Implementation Validation and Debug Tutorial<\/strong><br \/>\nThursday, September 10, 2015<br \/>\n1:30pm \u2013 3:00pm<br \/>\nDV Track, Sitara, The Leela Palace<br \/>\n<a href=\"http:\/\/dvcon-india.org\/conf\/program-at-a-glance\/\" target=\"_blank\" rel=\"noopener noreferrer\"><strong>More Information &gt;<\/strong><br \/>\n<\/a><a href=\"http:\/\/dvcon-india.org\/registration\/\" target=\"_blank\" rel=\"noopener noreferrer\"><strong>Register for this event &gt;<\/strong><\/a><\/li>\n<\/ul>\n<p>The papers on day 2 are primarily split into 3 parallel tracks, one on DV track and 2 parallel tracks on ESL. Within the DV track, one area is dedicated to UVM\/SV. The other categories within the DV track will cover Portable Stimulus &amp; Graph Based Stimulus, AMS, SoC &amp; Stimulus Generation, Emulation, Acceleration and Prototyping &amp; a generic selected category. The surprise among the categories is Portable Stimulus, which was a tutorial in last year however has continued to be of high interest and sessions will build on last year\u2019s initial tutorial.<\/p>\n<p>Overall there is an exciting mix of keynotes, tutorials, panels, papers and posters, which will make two exceptional days of learning, networking and fun. I look forward to seeing at DVCon India, 2015 and if you see me at the show, please come say hello and let me know what you think of the conference.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>I have always been wanting to contribute to the growing verification engineering community in India, which Mentor\u2019s CEO Wally Rhines&#8230;<\/p>\n","protected":false},"author":71604,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[325,442,446,457,467,497,638,787,819],"industry":[],"product":[],"coauthors":[],"class_list":["post-11901","post","type-post","status-publish","format-standard","hentry","category-news","tag-acceleration","tag-dvcon","tag-dvcon-india","tag-emulation","tag-esl","tag-fpga-debug","tag-portable-stimulus","tag-uvm","tag-verification"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/11901","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71604"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=11901"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/11901\/revisions"}],"predecessor-version":[{"id":19804,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/11901\/revisions\/19804"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=11901"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=11901"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=11901"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=11901"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=11901"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=11901"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}