{"id":11429,"date":"2015-04-03T16:04:31","date_gmt":"2015-04-03T23:04:31","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=11429"},"modified":"2026-03-27T08:42:55","modified_gmt":"2026-03-27T12:42:55","slug":"20-years-ago-10-years-ago-tomorrow-dac","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2015\/04\/03\/20-years-ago-10-years-ago-tomorrow-dac\/","title":{"rendered":"20 Years Ago \u2013 10 Years Ago \u2013 Tomorrow (DAC)"},"content":{"rendered":"

It is always good to pause to recognize the companies and individuals with whom we collaborate to create the verification flows and solutions that allow the simplest and most complex devices and systems to come to life.\u00a0 It is this time of year when the fruit of collaboration has generally been shared publicly.\u00a0 This is probably the case, in no small part, to the nearing of the annual trek to the Design Automation Conference (DAC<\/strong><\/a>).\u00a0 As we get closer to that week in June this year, I will discuss it even more.\u00a0 But now I would like to offer a look back at two major milestones around this time of the year that shaped our future.<\/p>\n

20 Years Ago<\/h3>\n

On April 3, 1995, we announced \u201cDevice Vendors Providing Library Support to Mentor.\u201d\u00a0 Our ModelSim simulator gained support from 12 ASIC and programmable logic vendors.\u00a0 Until then, Mentor\u2019s gate-level simulation was provided by QuickSim and its large collection of ASIC vendor libraries and flows.\u00a0 With the emergence of VITAL (VHDL Initiative Towards ASIC Libraries) and as an IEEE standards project for it (1976.4) emerged, we continued our activities to drive knowledge about VITAL and educate and help the rest of the ASIC vendor community so they could bring to market their own simulation libraries for ModelSim.<\/p>\n

As we added Verilog to the language mix, those Verilog libraries were likewise qualified and offered to the mutual customers we shared with our valued ASIC Vendor partners.\u00a0 ModelSim grew to be a very popular product and the value of collaboration taught us the importance of shared collaboration.<\/p>\n

10 Years Ago<\/h3>\n

In mid May 2005, we launched our Questa Vanguard Partnership (QVP) program modeled on the ModelSim program.\u00a0 SystemVerilog 3.1a had been released by Accellera and was in the final stages of IEEE certification which was to come in November 2005.\u00a0 But to get a jump on solidifying business relationships with our partners and to encourage support of SystemVerilog we began to work with companies around the world who expressed an interest to build a vibrant ecosystem.\u00a0 A lot was accomplished in the six months between the launch of the QVP program to the approval of the first IEEE SystemVerliog 1800-2005 standard.<\/p>\n

But it was good to pause then too and celebrate the standard with our new Questa partners, our mainstay semiconductor library partners and competitors in Japan.\u00a0 Upon IEEE approval of the standard, Accellera in conjunction with the Big-3 EDA companies and CQ Publishing (Japan), held a \u201cHappy Birthday\u201d celebration reception.\u00a0 I have to offer special thanks to my friends at Synopsys for the idea.\u00a0 And, yes, we all know that this November will be lucky 10 years for SystemVerilog and we have already started to discuss what can be done at the annual fall standards meetings in Japan to celebrate this milestone.<\/p>\n

Tomorrow (DAC)<\/h3>\n

As I mentioned, the great thing about this time of the year is the planning for DAC.\u00a0 Many good things have happened in the last year.\u00a0 Last year, at Mentor Graphics\u2019 urging and our public commitment to donate technology, Accellera started a \u201cProposed Working Group\u201d on Portable Stimulus<\/em> to determine the viability of a standards project.\u00a0 Accellera formally approved the formation of the Portable Stimulus Working Group in December 2014.\u00a0 At the Verification Academy booth at DAC, we will certainly offer updates on this work and affirm our sustained commitment to the development of this standard.\u00a0 I will share full details about what, when and where for the Verification Academy booth at DAC later.<\/p>\n

But wait!\u00a0 There will probably be more.\u00a0 I can assure you, I will post a few more times during this final two-month journey to DAC.\u00a0 And as the daily program for the Verification Academy booth is finalized, I will share its content my thoughts on this.\u00a0 And as industry events, like the Accellera DAC Breakfast are finalized, I will make this part of my commentary on DAC 2015 as well.\u00a0 It seems this DAC will be a busy DAC.<\/p>\n

But this is something you can do now!\u00a0 If you don\u2019t know if you want to attend the technical program yet, you should at a minimum secure a free pass to the exhibit floor and access to some open industry events.\u00a0 If you register by May 19th, you can choose the \u201cI Love DAC\u201d registration<\/strong><\/a> \u2013 complements of ATopTech, Atrenta, and Calypto.\u00a0 After May 19th, it is no longer free.\u00a0 So why not register now?\u00a0 I look forward to seeing you at DAC.<\/p>\n","protected":false},"excerpt":{"rendered":"

It is always good to pause to recognize the companies and individuals with whom we collaborate to create the verification…<\/p>\n","protected":false},"author":71541,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[306,326,348,409,528,533,601,638,658,732,751,842],"industry":[],"product":[],"coauthors":[],"class_list":["post-11429","post","type-post","status-publish","format-standard","hentry","category-news","tag-1076-4","tag-accellera","tag-asic-libraries","tag-dac","tag-ieee","tag-ieee-1800","tag-modelsim","tag-portable-stimulus","tag-questa","tag-standards","tag-systemverilog","tag-vital"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/11429","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/users\/71541"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/comments?post=11429"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/11429\/revisions"}],"predecessor-version":[{"id":14595,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/posts\/11429\/revisions\/14595"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/media?parent=11429"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/categories?post=11429"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/tags?post=11429"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/industry?post=11429"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/product?post=11429"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/wp-json\/wp\/v2\/coauthors?post=11429"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}