{"id":11361,"date":"2015-03-11T12:07:48","date_gmt":"2015-03-11T19:07:48","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=11361"},"modified":"2026-03-27T08:35:51","modified_gmt":"2026-03-27T12:35:51","slug":"part-2-the-2014-wilson-research-group-functional-verification-study","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2015\/03\/11\/part-2-the-2014-wilson-research-group-functional-verification-study\/","title":{"rendered":"Part 2: The 2014 Wilson Research Group Functional Verification Study"},"content":{"rendered":"

FPGA Verification Effort Trends<\/strong><\/h2>\n

This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study (click here<\/a>). \u00a0In my previous blog (click here<\/a>), I focused on FPGA design trends. In this blog, I present findings from our study related to the effort spent in verification.<\/p>\n

Directly asking study participants how much effort they spend in verification will not work. The reason is that it\u2019s hard to find a paper or article on verification that doesn\u2019t start with the phrase: \u201cSeventy percent of a project\u2019s effort is spent in verification\u2026\u201d In other words, the industry is already biased to respond with this effort value. Yet, there are really no creditable references to quantify this value.<\/p>\n

I don\u2019t believe that there is a simple answer to the question, \u201cHow much effort was spent on verification in your last project?\u201d In fact, I believe that it is necessary to look at multiple data points derived from multiple questions to truly get a sense of effort spent in verification. And that\u2019s what we did in our functional verification study.<\/p>\n

Total FPGA Project Time Spent in Verification<\/strong><\/h3>\n

To try to assess the effort spent in verification, let\u2019s begin by looking at one data point, which is the total project time spent in verification. Figure 1 shows the trends in total percentage of FPGA project time spent in verification\u00a0by comparing the 2012 Wilson Research Group study (in dark blue), and the 2014 Wilson Research Group study (in light blue).<\/p>\n

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Figure 1. Percentage of FPGA project time spent in verification<\/strong><\/p>\n

Between the years 2012 and 2014 the industry did see a seven percent increase in the average time an FPGA project spends in verification. Historically, FPGA projects have spent less time in verification than ASIC\/IC projects. The FPGA project strategy has traditionally been to get to the lab as soon as possible, and then iterate on issues in the lab. In a future blog I\u2019ll show data that indicates this strategy does not necessarily yield good results in terms of meeting project schedule or quality objectives. Also, this lab-focused approach to FPGA verification becomes less effective as FPGA complexity increases.<\/p>\n

Peak Number of Design and Verification Engineers<\/strong><\/h3>\n

Perhaps one of the biggest challenges in design and verification today is identifying solutions to increase productivity and control engineering headcount. To illustrate the need for productivity improvement, we discuss the trend in terms of increasing engineering headcount for FPGA projects. Figure 2 shows the mean peak number of design and verification engineers working on an FPGA project. Again, this is an industry average since some projects have many engineers while other projects have few.<\/p>\n

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Figure 2. Mean peak number of engineers working on an FPGA project<\/strong><\/p>\n

You can see that the compounded annual growth rate (CAGR) for the peak number of FPGA design engineers between 2012 and 2014 was 4.9 percent, while the CAGR for the peak number of FPGA verification engineers was 20.9 percent. This huge demand for verification engineers on FPGA projects is one indicator of growing verification complexity in FPGA designs. Also, note that the ratio of design engineers versus verification engineers is approaching 1-to-1. This similar trend happened on traditional ASIC\/IC designs in 2012.<\/p>\n

In my next blog (click here<\/a>) I focus on the time that FPGA design and verification engineers spends in various task.<\/p>\n

Quick links to the 2014 Wilson Research Group Study results<\/h2>\n