{"id":11295,"date":"2015-02-08T14:57:42","date_gmt":"2015-02-08T21:57:42","guid":{"rendered":"https:\/\/blogs.mentor.com\/verificationhorizons\/?p=11295"},"modified":"2026-03-27T08:35:41","modified_gmt":"2026-03-27T12:35:41","slug":"part-1-the-2014-wilson-research-group-functional-verification-study","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/verificationhorizons\/2015\/02\/08\/part-1-the-2014-wilson-research-group-functional-verification-study\/","title":{"rendered":"Part 1: The 2014 Wilson Research Group Functional Verification Study"},"content":{"rendered":"

FPGA Design Trends<\/h3>\n

In my previous blog, I introduced the 2014 Wilson Research Group Functional Verification Study (click here<\/a>). The\u00a0objective of my previous blog was to provide an overview on our large, worldwide industry study. The key findings\u00a0from this study will be presented in a set of upcoming blogs. In this blog, I present trends related to various aspects of FPGA design to illustrate growing design complexity.<\/p>\n

Let\u2019s begin by examining embedded processor trends targeted at a general FPGA implementation. Our 2014 study found that 56% of all FPGA designs contained one or more embedded processors, as shown in Figure 1. Although we did not see an overall growth in the number of FPGAs containing one or more embedded processors between 2012 and 2014, we did see an increase in the number of FPGA projects creating designs containing more than one embedded processor.<\/p>\n

\"2014-WRG-BLOG-FPGA-1-1\"<\/a><\/p>\n

Figure 1. Number of embedded processors in FPGA trends<\/strong><\/p>\n

SoC class designs (i.e., designs containing embedded processors) add a new layer of verification complexity to the verification process that did not exist with traditional non-SoC class designs due to hardware and software interactions, new coherency architectures, and the emergence of complex network-on-a-chip interconnect.<\/p>\n

In addition to embedded processors targeted at general FPGA class of designs, there has been a recent emergence of specific programmable SoC FPGA implementations, such as: Xilinx\u2019s Zynq, Altera\u2019s Arria\/Cydone, and Microsemi\u2019s SmarFusion. Figure 2 shows the adoption trends for these programmable SoC FPGAs, which you can see grew by over 93 percent between 2012 and 2014. Keep in mind that this trend data does not represent volume production\u2014it represents the number of FPGA projects that are creating designs targeted at a programmable SoC class of FPGA.<\/p>\n

\"2014-WRG-BLOG-FPGA-1-3\"<\/a><\/p>\n

Figure 2. Type of FPGA implementation trends<\/strong><\/p>\n

As the industry moves to SoC class designs, regardless of targeted FPGA implementation, FPGA projects are starting to increase\u00a0their adoption of industry standard on-chip bus protocols\u2014versus proprietary bus protocols. Figure 3 shows the current adoption of AMBA and other on-chip bus protocols for FPGA designs as identified by our new study. Note, the reason we are not showing trends here is that the 2012 study did not separate out the various AMBA protocols, which is something we decided to do for our 2014 study. Hence, we cannot do an apples-to-apples comparison between 2012 and 2014 for FPGA on-chip bus protocol adoption.<\/p>\n

\"2014-WRG-BLOG-FPGA-1-3a\"<\/a><\/p>\n

Figure 3. FPGA on-chip bus protocol adoption<\/strong><\/p>\n

Another aspect of SoC class design is the emergence of IP-based design practices, which is fundamental for improving design productivity. Figure 4 shows FPGA design composition trends\u2014and we see that there has been a declined in new logic created by FPGA project teams. At the same time we see an increase in the adoption of both internally developed and externally acquired IP.<\/p>\n

\"2014-WRG-BLOG-FPGA-1-5\"<\/a><\/p>\n

Figure 4. FPGA design composition trends<\/strong><\/p>\n

In my next blog (click here<\/a>), I\u2019ll focus on verification effort trends related to FPGA designs.<\/p>\n

Quick links to the 2014 Wilson Research Group Study results<\/h2>\n